Intel Field Programmable Gate Arrays Research Articles

Hybrid ALM-DSP TDC in Intel Arria 10 FPGA

The article presents the first implementation of a time-to-digital converter (TDC) using a digital signal processing (DSP) block from an Intel field-programmable gate array (FPGA) device. The design and configuration capabilities of the DSP blocks of the leading FPGA manufacturers, AMD and Intel, are compared in the context of time/digital conversion. Next, three variants of TDCs are presented. The problem of ultra-wide bins observed in both the classic version of the converter based on the Adaptive Logic Modules (ALM) and the version built using only DSP blocks has been mitigated in a hybrid variant, combining both solutions. The proposed variant of the hybrid ALM-DSP TDC implemented in Arria 10 FPGA from Intel (20 nm process node) achieved a resolution of 2.1 ps, a single-shot-precision better than 6.36 ps and reduced the maximum differential nonlinearity (DNL) error from 74.5 ps to 12.7 ps.

Accelerating electrostatic particle-in-cell simulation: A novel FPGA-based approach for efficient plasma investigations.

Particle-in-cell (PIC) simulation serves as a widely employed method for investigating plasma, a prevalent state of matter in the universe. This simulation approach is instrumental in exploring characteristics such as particle acceleration by turbulence and fluid, as well as delving into the properties of plasma at both the kinetic scale and macroscopic processes. However, the simulation itself imposes a significant computational burden. This research proposes a novel implementation approach to address the computationally intensive phase of the electrostatic PIC simulation, specifically the Particle-to-Interpolation phase. This is achieved by utilizing a high-speed Field Programmable Gate Array (FPGA) computation platform. The suggested approach incorporates various optimization techniques and diminishes memory access latency by leveraging the flexibility and performance attributes of the Intel FPGA device. The results obtained from our study highlight the effectiveness of the proposed design, showcasing the capability to execute hundreds of functional operations in each clock cycle. This stands in contrast to the limited operations performed in a general-purpose single-core computation platform (CPU). The suggested hardware approach is also scalable and can be deployed on more advanced FPGAs with higher capabilities, resulting in a significant improvement in performance.

X-ray Tomography Reconstruction Accelerated on FPGA through High-Level Synthesis Tools.

Model-Based Iterative Reconstruction (MBIR) algorithms iteratively use expensive computational operators of forward and backward projections. The irregular memory access pattern of these operators makes them a memory-bound application. Their computation time must be reduced to meet clinical routine constraints. This paper proposes a hardware accelerator architecture based on Field Programmable Gate Arrays (FPGAs) through high-level language, as an alternative to GPU architecture. This acceleration is based on an offline memory access analysis to address the main bottleneck of the algorithm and maximize the data reuse rate. The offline analysis allows for the tuning of the architecture parameters so that they converge to an optimal solution. Then, the Berkeley Roofline model guides our optimization steps by iteratively analyzing the design performance. Our design flow significantly improved the algorithm's computational intensity and overcame the memory bottleneck. Thus, our architecture takes advantage of the FPGA local memory to achieve significant memory bandwidth and efficiently harness the pipeline without stalling the computation. Furthermore, we present the scaling-up strategy from mid-range FPGA to high-end FPGA and any concerns of portability. We used two Intel FPGA devices to implement the algorithm, and then we compared the results with our GPU implementation in terms of speedup and energy efficiency. Our experimental results show that our design has achieved better computational throughput than the works on FPGA architectures reported in the literature.

Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study

The improved k-nearest neighbor (KNN) algorithm based on class contribution and feature weighting (DCT-KNN) is a highly accurate approach. However, it requires complex computational steps which consumes much time for the classification process. A field programmable gate array (FPGA) can be used to solve this drawback. However, using traditional hardware description language (HDL) to implement FPGA-based accelerators requires a high design time. Fortunately, the open computing language (OpenCL) high level parallel programming tool allows rapid and effective design on FPGA-based hardware accelerators. In this study, OpenCL has been used to examine speeding up the DCT-KNN algorithm on the FPGA parallel computing platform through applying numerous parallelization and optimization techniques. The optimized approach of the improved KNN could be used in various engineering problems that require a high speed of classification process. Classification of the COVID-19 disease is the case study used to examine this work. The experimental results show that implementing the DCT-KNN algorithm on the FPGA platform (Intel De5a-net Arria-10 device was used) gives an extremely high performance when compared to the traditional single-core-CPU based implementation. The execution time for our optimized design on the FPGA accelerator is 44 times faster than the conventional design implemented on the regular CPU-based computational platform.

Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model.

Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (±360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.

FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5G NR) communication systems. Simulation effort further increases when using more realistic geometry-based channel models, such as the three-dimensional spatial channel model (3D-SCM). Channel emulation is used for functional and performance verification of such models in the network planning phase. These models use multiple finite impulse response (FIR) filters and have a very high degree of parallelism which can be exploited for accelerated execution on Field Programmable Gate Array (FPGA) and Graphics Processing Unit (GPU) platforms. This paper proposes an efficient re-configurable implementation of the 3rd generation partnership project (3GPP) 3D-SCM on FPGAs using a design flow based on high-level synthesis (HLS). It studies the effect of various HLS optimization techniques on the total latency and hardware resource utilization on Xilinx Alveo U280 and Intel Arria 10GX 1150 high-performance FPGAs, using in both cases the commercial HLS tools of the producer. The channel model accuracy is preserved using double precision floating point arithmetic. This work analyzes in detail the effort to target the FPGA platforms using HLS tools, both in terms of common parallelization effort (shared by both FPGAs), and in terms of platform-specific effort, different for Xilinx and Intel FPGAs. Compared to the baseline general-purpose central processing unit (CPU) implementation, the achieved speedups are 65X and 95X using the Xilinx UltraScale+ and Intel Arria FPGA platform respectively, when using a Double Data Rate (DDR) memory interface. The FPGA-based designs also achieved ~3X better performance compared to a similar technology node NVIDIA GeForce GTX 1070 GPU, while consuming ~4X less energy. The FPGA implementation speedup improves up to 173X over the CPU baseline when using the Xilinx UltraRAM (URAM) and High-Bandwidth Memory (HBM) resources, also achieving 6X lower latency and 12X lower energy consumption than the GPU implementation.

GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Memristive technology is a promising game-changer in computers and electronics. In this paper, a system exploring the optimal paths through a maze, utilizing a memristor-based setup, is developed and concreted on a FPGA (field-programmable gate array) device. As a memristor, a digital emulator has been used. According to the proposed approach, the memristor is used as a delay element, further configuring the test graph as a memristor network. A parallel algorithm is then applied, successfully reducing computing time and increasing the system’s efficiency. The proposed system is simple, easy to scale up and capable of implementing different graph configurations. The operation of the algorithm in the MATLAB (matrix laboratory) programming enviroment is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases, reliable results are obtained quickly and conveniently, even for the case of a 300 × 300 nodes maze.

Design of an FPGA-Based Fuzzy Feedback Controller for Closed-Loop FES in Knee Joint Model.

Functional electrical stimulation (FES) device has been widely used by spinal cord injury (SCI) patients in their rehab exercises to restore motor function to their paralysed muscles. The major challenge of muscle contraction induced by FES is early muscle fatigue due to the open-loop stimulation strategy. To reduce the early muscle fatigue phenomenon, a closed-loop FES system is proposed to track the angle of the limb’s movement and provide an accurate amount of charge according to the desired reference angle. Among the existing feedback controllers, fuzzy logic controller (FLC) has been found to exhibit good control performance in handling complex non-linear systems without developing any complex mathematical model. Recently, there has been considerable interest in the implementation of FLC in hardware embedded systems. Therefore, in this paper, a digital fuzzy feedback controller (FFC) embedded in a field-programmable gate array (FPGA) board was proposed. The digital FFC mainly consists of an analog-to-digital converter (ADC) Data Acquisition and FLC sub-modules. The FFC was designed to monitor and control the progress of knee extension movement by regulating the stimulus pulse width duration to meet the target angle. The knee is expected to extend to a maximum reference angle setting (70°, 40° or 30°) from its normal position of 0° once the stimulus charge is applied to the muscle by the FES device. Initially, the FLC was modelled using MATLAB Simulink. Then, the FLC was hardcoded into digital logic using hardware description language (HDL) Verilog codes. Thereafter, the performance of the digital FLC was tested with a knee extension model using the HDL co-simulation technique in MATLAB Simulink. Finally, for real-time verification, the designed digital FFC was downloaded to the Intel FPGA (DE2-115) board. The digital FFC utilized only 4% of the total FPGA (Cyclone IV E) logic elements (LEs) and required 238 µs to regulate stimulus pulse width data, including 3 µs for the FLC computation. The high processing speed of the digital FFC enables the stimulus pulse width duration to be updated every stimulation cycle. Furthermore, the implemented digital FFC has demonstrated good control performance in accurately controlling the stimulus pulse width duration to reach the desired reference angle with very small overshoot (1.4°) and steady-state error (0.4°). These promising results are very useful for a real-world closed-loop FES application.

Algorithmic TCAM on FPGA with data collision approach

<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.</span>

An OpenCL-based parallel acceleration of aSobel edge detection algorithm Using IntelFPGA technology

This paper examines the feasibility of using commercial out-of-the-box Reconfigurable Field Programmable Gate Array (FPGA) technology and the OpenCL framework to create efficient Sobel edge-detection implementation, which is considered a fundamental part in the field of image and video processing. The revised proposed approach was created at a high level of abstraction and executed on high commodity Intel FPGA platform. This was performed in a manner that was designed to allow the high-level compiler/synthesis tool to manipulate a task a parallelism model. The most promising FPGA and the naive implementations were compared to their single-core CPU software equivalents while manipulating local-memory, pipelining, loop unrolling, vectorization, internal channels mechanisms and memory coalescing to provide a much more effective hardware design. The run-time and the power consumption attributes were estimated for each implementation. The proposed FPGA based implementations were found to have significantly better runtime and power consumption with approximately up to 37 folds of improvement in the whole execution/transfer time, and up to 53 folds of improvement in energy consumption when compared to a specific single-core CPU based implementation.

A methodology to standardize the development of FPGA-based high-performance DAQ and processing systems using OpenCL

Abstract The development of high-performance data acquisition (DAQ) and processing systems is crucial for the next-generation diagnostics used in big science experiments. In the ITER experiment, the instrumentation, control hardware, and software architecture selected for this type of application is called a fast controller. The core element of a fast controller is a chassis based on the use of the PCIe eXtension for Instrumentation (PXIe) or Micro Telecommunication Computing Architecture (MTCA). This paper presents a software framework named IRIO-OpenCL that was developed using the ITER CODAC Core System (CCS) Linux-based distribution, oriented toward the development of field-programmable gate array (FPGA)-based DAQ systems using OpenCL. State-of-the-art DAQ-FPGA systems are developed using hardware description languages (HDLs). The approach used in IRIO-OpenCL simplifies DAQ to enable the user to write C-like processing algorithms with OpenCL, minimizing the use of HDLs. The software has been implemented in C++ following ITER’s Nominal Device Support v3 (NDSv3) model that abstracts and generalizes the development of software device drivers and simplifies the interface with the Experimental Physics and Industrial Control System (EPICS). The framework has been validated in an ITER fast controller including an MTCA.4 chassis with an advanced mezzanine card (AMC) module using an Arria 10 FPGA from Intel FPGA and an FPGA mezzanine card (FMC) DAQ module from Analog Devices. The developed application solves the DAQ and processing problems associated with the neutron flux measurement and achieves a sampling rate of 1 GS/s using approximately 40 % of the FPGA resources. The methodology proposed in this paper reduces the development time of these systems while maintaining high performance.

Hardware Implementation and Quantization of Tiny-Yolo-v2 using Open CL

The trend of increasingly model size in Deep Neural Network (DNN) algorithms boost the performance of visual recognition tasks. These gains in performance have come at a cost of increase in computational complexity and memory bandwidth. Recent studies have explored the fixed-point implementation of DNN algorithms such as AlexNet and VGG on Field Programmable Gate Array (FPGA) to facilitate the potential of deployment on embedded system. However, there are still lacking research on DNN object detection algorithms on FPGA. Consequently, we propose the implementation of Tiny-Yolo-v2 on Cyclone V PCIe FPGA board using the High-Level Synthesis Tool: Intel FPGA Software Development Kit (SDK) for OpenCL. In this work, a systematic approach is proposed to convert the floating point Tiny-Yolo-v2 algorithms into 8-bit fixed-point. Our experiments show that the 8-bit fixed-point Tiny-Yolo-v2 have significantly reduce the hardware consumption with only 0.3% loss in accuracy. Finally, our implementation achieves peak performance of 31.34 Giga Operation per Second (GOPS) and comparable performance density of 0.28GOPs/DSP to prior works under 120MHz working frequency.

Low-Power and High-Speed Deep FPGA Inference Engines for Weed Classification at the Edge

Deep neural networks (DNNs) have recently achieved remarkable performance in a myriad of applications, ranging from image recognition to language processing. Training such networks on graphics processing units (GPUs) currently offers unmatched levels of performance; however, GPUs are subject to large-power requirements. With recent advancements in high-level synthesis (HLS) techniques, new methods for accelerating deep networks using field programmable gate arrays (FPGAs) are emerging. FPGA-based DNNs present substantial advantages in energy efficiency over conventional CPU- and GPU-accelerated networks. Using the Intel FPGA software development kit (SDK) for OpenCL development environment, networks described using the high-level OpenCL framework can be accelerated targeting heterogeneous platforms including CPUs, GPUs, and FPGAs. These networks, if properly customized on GPUs and FPGAs, can be ideal candidates for learning and inference in resource-constrained portable devices such as robots and the Internet of Things (IoT) edge devices, where power is limited and performance is critical. Here, we introduce GPU- and FPGA-accelerated deterministically binarized DNNs, tailored toward weed species classification for robotic weed control. Our developed networks are trained and benchmarked using a publicly available weed species dataset, named DeepWeeds, which include close to 18 000 weed images. We demonstrate that our FPGA-accelerated binarized networks significantly outperform their GPU-accelerated counterparts, achieving a>7-fold decrease in power consumption, while performing inference on weed images 2.86 times faster compared to our best performing baseline full-precision GPU implementation. These significant benefits are gained whilst losing only 1.17% of validation accuracy. In this paper, this is a significant step toward enabling deep inference and learning on IoT edge devices, and smart portable machines such as agricultural robots, which is the target application.

Fixed Point Implementation of Tiny-Yolo-v2 using OpenCL on FPGA

Deep Convolutional Neural Network (CNN) algorithm has recently gained popularity in many applications such as image classification, video analytic and object detection. Being compute-intensive and memory expensive, CNN-based algorithms are hard to be implemented on the embedded device. Although recent studies have explored the hardware implementation of CNN-based object classification models such as AlexNet and VGG, there is still a rare implementation of CNN-based object detection model on Field Programmable Gate Array (FPGA). Consequently, this study proposes the fixed-point (16-bit) implementation of CNN-based object detection model: Tiny-Yolo-v2 on Cyclone V PCIe Development Kit FPGA board using High-Level-Synthesis (HLS) tool: OpenCL. Considering FPGA resource constraints in term of computational resources, memory bandwidth, and on-chip memory, a data pre-processing approach is proposed to merge the batch normalization into convolution layer. To the best of our knowledge, this is the first implementation of Tiny-Yolo-v2 object detection algorithm on FPGA using Intel FPGA Software Development Kit (SDK) for OpenCL. Finally, the proposed implementation achieves a peak performance of 21 GOPs under 100 MHz working frequency.

Characteristic features of LUT setting codes of Intel FPGAs

State-of-the-art digital circuit design widely uses field programmable gate arrays (FPGAs), in which the functions of logic cells and their connections are set up. That is defined in the configuration file that is loaded in the configuration memory cells (static random access memory) of FPGA from external memory. The logic itself is implemented in the so-called LUTs (Look Up Tables), multiplexors that implement memory cells, are based on transmitting transistors and represents a tree that is activated by a specific variable collection. The setting is multiplexor data, therefore logical (switching) function values for the specific collection are transmitted to the tree output. As it turns out, the associated LUT setting code can be decoded and used for analyzing synthesis results in Quartus II by Altera that has been acquired by Intel. Now Intel also specializes in FPGA production. The article considers an example of the synthesis of a simple combinational finite state machine that implements the so-called majority function (2 out of 3). This function equals 1 if the majority of variables equals 1. Majority function implementation diagram is synthesized in Quartus II that builds a special BDF (Block Diagram/Schematic File) file. The resulting diagram is examined with Map Viewer. In the appropriate diagram, LUT (Logic Cell Comb) setting codes for implementation of the specified function are set forth in the form of four-digit hexacodes. Decoding is shown for setting codes for logic cells of FPGA LUT type that describe the content of the respective truth tables of functions that depend on the input variable machine. The article shows the code changes in the process of diagram optimization by Quartus II with possible modification of the variables sequence order and correspondence with the inputs of a four-input LUT without modifications to the logical function. If Stratix IIGX FPGA is used that has the so-called adaptive logic modules (ALM) with 6 inputs, Quartus II uses 64-bit codes (eight-digit hexacodes). Respective coding is also examined in this paper.