Hybrid ALM-DSP TDC in Intel Arria 10 FPGA

Abstract

The article presents the first implementation of a time-to-digital converter (TDC) using a digital signal processing (DSP) block from an Intel field-programmable gate array (FPGA) device. The design and configuration capabilities of the DSP blocks of the leading FPGA manufacturers, AMD and Intel, are compared in the context of time/digital conversion. Next, three variants of TDCs are presented. The problem of ultra-wide bins observed in both the classic version of the converter based on the Adaptive Logic Modules (ALM) and the version built using only DSP blocks has been mitigated in a hybrid variant, combining both solutions. The proposed variant of the hybrid ALM-DSP TDC implemented in Arria 10 FPGA from Intel (20 nm process node) achieved a resolution of 2.1 ps, a single-shot-precision better than 6.36 ps and reduced the maximum differential nonlinearity (DNL) error from 74.5 ps to 12.7 ps.