A methodology to standardize the development of FPGA-based high-performance DAQ and processing systems using OpenCL

Abstract

Abstract The development of high-performance data acquisition (DAQ) and processing systems is crucial for the next-generation diagnostics used in big science experiments. In the ITER experiment, the instrumentation, control hardware, and software architecture selected for this type of application is called a fast controller. The core element of a fast controller is a chassis based on the use of the PCIe eXtension for Instrumentation (PXIe) or Micro Telecommunication Computing Architecture (MTCA). This paper presents a software framework named IRIO-OpenCL that was developed using the ITER CODAC Core System (CCS) Linux-based distribution, oriented toward the development of field-programmable gate array (FPGA)-based DAQ systems using OpenCL. State-of-the-art DAQ-FPGA systems are developed using hardware description languages (HDLs). The approach used in IRIO-OpenCL simplifies DAQ to enable the user to write C-like processing algorithms with OpenCL, minimizing the use of HDLs. The software has been implemented in C++ following ITER’s Nominal Device Support v3 (NDSv3) model that abstracts and generalizes the development of software device drivers and simplifies the interface with the Experimental Physics and Industrial Control System (EPICS). The framework has been validated in an ITER fast controller including an MTCA.4 chassis with an advanced mezzanine card (AMC) module using an Arria 10 FPGA from Intel FPGA and an FPGA mezzanine card (FMC) DAQ module from Analog Devices. The developed application solves the DAQ and processing problems associated with the neutron flux measurement and achieves a sampling rate of 1 GS/s using approximately 40 % of the FPGA resources. The methodology proposed in this paper reduces the development time of these systems while maintaining high performance.