Integral Nonlinearity Research Articles

An Energy-Efficient SAR ADC With Event-Triggered Error Correction

This brief presents an energy-efficient fully differential 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with a resolution of 10 bits and a sampling rate of 320 kS/s. The optimal capacitor split and bypass number is analyzed to achieve the highest switching energy efficiency. The common-mode voltage level remains constant during the MSB-capacitor switching cycles. To minimize nonlinearity due to charge averaging voltage offset or DAC array mismatch, an event-triggered error correction method is employed as a redundant cycle for detecting digital code errors within 1 least significant bit (LSB). A test chip was fabricated using the 180-nm CMOS process and occupied a 0.0564-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. Under a regular 0.65-V supply voltage, the ADC achieved an effective number of bits of 9.61 bits and a figure of merit (FOM) of 6.38 fJ/conversion step, with 1.6-μW power dissipation for a low-frequency input. The measured differential and integral nonlinearity results are within 0.30 LSB and 0.43 LSB, respectively.

An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method

A novel ultrafast and low-cost pipelined analog-to-digital converter (ADC) testing and calibration method is proposed. The ADC nonlinearities are modeled as segmented parameters with interstage gain errors. During the test phase, a pure sine wave is sent as input and the model parameters are estimated from the output data with the system identification method. Significantly, fewer samples are required when compared to traditional histogram testing. The modeled errors are then removed from the digital output codes during the calibration phase. Extensive simulations have been run to verify the correctness and robustness of the proposed method. With just 4000 samples, a 12-bit ADC can be accurately tested and calibrated to achieve less than 1 least significant bit (LSB) integral nonlinearity (INL). Measurement results show that the ADC effective number of bits (ENOB) is improved from 9.7to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by 20 dB after calibration. The chip is fabricated in 40-nm technology and consumes 10.71 mW at a sampling rate of 125 MS/s.

64 × 64 GM-APD array-based readout integrated circuit for 3D imaging applications

Using the high sensitivity of the avalanche photodiode (APD) detector operated in the Geiger-mode (GM), an array readout integrated circuit (ROIC) comprising a two-segment time-to-digital converter (TDC) is employed for wide-dynamic time interval measurement, where a 1-bit low-segment TDC is implemented by discriminating a single-phase clock period. The proposed 64 $\times$ 64 GM-APD array ROIC fabricated using Taiwan semiconductor manufacturing company (TSMC) 0.18-$\mu~$m complementary metal oxide semiconductor (CMOS) technology can operate at a maximum frequency of 500 MHz provided by an external phase-locked loop clock. The time resolution is reduced to $<1$ ns along with a maximum range of 4 $\mu~$s; the differential non-linearity (DNL) and integral non-linearity (INL) are restricted to approximately $-$0.15 to 0.15 least significant bit (LSB) and $-$0.3 to 0.32 LSB, respectively; and the power consumption is 490 mW under a frame rate of 20 kHz. The developed ROIC is successfully used in imaging applications in two different ways.

Rapid calibration of bits weights error for high‐resolution successive approximation register ADC

This study presents the rapid calibration of bits weights error for an 18 bit successive approximation register analogue-to-digital converter (ADC). This calibration technique is a new hybrid algorithm. Comparing to the traditional methods, this technique significantly reduces the convergence time and improves the accuracy of bits weights error estimation. There is no wasteful time in the correction process. This proposed approach estimates the bits weights error not only from the digital-to-analogue converter capacitor mismatch, inter-stage gain error, but also the metal insulator metal (MIM), capacitor second-order voltage coefficient in the ultra-high-resolution ADC. The proposed algorithm has been verified with a test 18 bit ADC chip, where measured results show the calibration is able to improve the peak integral nonlinearity (INL), of the ADC from 29 to 1.0 LSB after calibration. Measured results also show the signal-to-noise and distortion ratio/spurious-free dynamic range of the ADC improves from 83/94 to 96/127 dB after calibration. It will be seen that the calibration is achieved in ∼4k cycles, which is more than ×25 faster than previously published algorithm.

A $192\times128$ Time Correlated SPAD Image Sensor in 40-nm CMOS Technology

A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$192 \times 128$ </tex-math></inline-formula> pixel single photon avalanche diode (SPAD) time-resolved single photon counting (TCSPC) image sensor is implemented in STMicroelectronics 40-nm CMOS technology. The 13% fill factor, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$18.4\,\,\mu \text {m} \times 9.2\,\,\mu \text{m}$ </tex-math></inline-formula> pixel contains a 33-ps resolution, 135-ns full scale, 12-bit time-to-digital converter (TDC) with 0.9-LSB differential and 5.64-LSB integral nonlinearity (DNL/INL). The sensor achieves a mean 219-ps full-width half-maximum (FWHM) impulse response function (IRF) and is operable at up to 18.6 kframes/s through 64 parallelized serial outputs. Cylindrical microlenses with a concentration factor of 3.25 increase the fill factor to 42%. The median dark count rate (DCR) is 25 Hz at 1.5-V excess bias. A digital calibration scheme integrated into a column of the imager allows off-chip digital process, voltage, and temperature (PVT) compensation of every frame on the fly. Fluorescence lifetime imaging microscopy (FLIM) results are presented.

A 550-$\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS

This paper presents an incremental analog-todigital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signalto-quantization-noise ratio (SQNR) exponentially with a few number of clock cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniformexponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 μW, and 0.134 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/-0.27 LSB and +0.84 LSB/-0.81 LSB, respectively.

A 1.0 V, 9.84 fJ/c-s FOM reconfigurable hybrid SAR-sigma delta ADC for signal processing applications

In this paper, a novel, low power, 16-bit, 9.84 fJ/conv-step FOM, reconfigurable, hybrid SAR-sigma delta ADC is presented. The ADC has been designed and implemented with two stages of programmable 4-bit SAR ADC followed by an 8-bit first order incremental sigma delta ADC. The resolution (which is reconfigurable), power and performance are controlled statically to get 12-bit, 14-bit, 16-bit operation. To minimize the power consumption, opamp turnoff technique is implemented between the stages. Mathematical modeling of the design is carried out using MATLAB SIMULINK. The ADC is fabricated in global foundries 180 nm CMOS process and results presented are those actually measured. In terms of performance, the IC has a differential non-linearity of ± 0.25 LSB, integral non-linearity of ± 0.51 LSB, signal-to-noise distortion ratio of 91.1 dB and spurious-free dynamic range of 99.4 dB. The Walden and Schreier figures of merit (FOMW and FOMS) at 1.6 MHz sampling frequency are 9.84 fJ/conversion-step and 183.6 dB respectively. Power consumption is measured to be 478 µW @ 1.0 V supply voltage and the total core area is found to be 0.15 mm2.

A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

Modeling of ADC-Based Serial Link Receivers With Embedded and Digital Equalization

Serial link receivers with high-speed analog-to-digital converters (ADCs) can utilize powerful digital-domain equalizers and support multilevel modulation schemes. This paper presents a hybrid statistical modeling framework for ADC-based serial link receivers. The framework builds upon the existing statistical modeling techniques for mixed-signal receivers and adds the support of ADC quantization noise, radix errors [integral nonlinearity and differential nonlinearity (INL/DNL)], and time-interleaving mismatches. A rapid purely statistical simulation mode is utilized to model systems with small front-end nonlinearity and ADC INL/DNL. To include ADC INL/DNL, a hybrid approach is presented with an initial short transient simulation. The presented modeling framework is used to explore the effectiveness of embedding an analog feed-forward equalizer (FFE) in the ADC of a 10-Gb/s receiver. Measurement results of a 10-Gb/s ADC-based receiver prototype with a three-tap embedded FFE in the ADC and a digital four-tap FFE and three-tap decision feedback equalizer are presented to validate the presented framework.

Histogram‐based mixed‐signal time‐to‐digital‐converter array for direct time‐of‐flight depth sensors

This Letter introduces a histogram-based time-to-digital-converter (TDC) array for direct time-of-flight depth sensors. The 12-bit TDC array measures the time of flight (TOF) of a light pulse that is detected using an external single-photon avalanche diode (SPAD) array. As SPADs are noisy owing to dark electrons and scattered photons, statistical measurements based on histograms are essential, but require a large memory. In this work, the authors propose a mixed-signal TDC with an integrated histogram generation unit (HGU) that reduces memory requirement significantly as well as filters out invalid TOF readings. In addition, for application of the high-resolution SPAD array, an area-efficient TDC array with high uniformity was implemented by the proposed phase-dependent latching and temporal double sampling schemes. The prototype chip was fabricated using a 180 nm CMOS process, including 8-channel TDCs. The measurements show an integral non-linearity (INL)/a differential nonlinearity (DNL) of 0.76/0.49 least significant bit (LSB) and high uniformity under 0.19 LSB. The HGU was designed off-chip for prior verification, and was post-simulated with the measured TOF from the fabricated chip. Using the histogram-based TDC, the authors could detect an object located at a distance of 3 m accurately while reducing memory requirement by more than 128 times.

A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR Filter

This paper presents a compact 10-b successive approximation register analog-to-digital converter (SAR ADC) in 65-nm CMOS with an integrated passive finite impulse response (FIR) filter for anti-aliasing. Conventional switched-capacitor digital-to-analog converters (DACs) are usually implemented with unit elements for the best matching performance, at the cost of increased chip area. Instead, this paper proposes a unit-length capacitor implementation, which minimizes the number of components and thus minimizes area, while also achieving good linearity (integral non-linearity of 0.39 LSB, differential non-linearity of 0.55 LSB, and SFDR of 75 dB) despite using a small LSB capacitor of 125 aF. The 10-b SAR ADC occupies only $36 \times 36\,\,\mu \text{m}$ , thanks to the small-size DAC, and by placing the ADC circuits directly under the capacitors. The ADC was tested at 10 and 30 MS/s and achieves an effective number of bits of 9.18/9.10 bit with an figure-of-merit of 4.1/4.4 fJ per conversion-step, respectively. Besides the ADC, a passive analog FIR filter is added to implement an anti-aliasing filter. The topology is based on a passive charge-sharing network and thus only consumes power for the clock phase generation and switch drivers. A 4 $\times $ time-interleaved 15-tap passive FIR filter is implemented, which can realize >42 dB out-of-band rejection and 4 $\times $ decimation while occupying only $53\times 90\,\,\mu \text{m}$ . The filter and the ADC together consume 39.2 $\mu \text{W}$ for an output rate of 10 MS/s.

A Low Complexity Digital Foreground Calibration Technique for CMOS Pipelined ADCs

A low complexity all-digital foreground calibration technique to correct linear and nonlinear errors is proposed for pipeline ADCs in this paper. This method based on the integral nonlinearity (INL) piecewise least-squares fitting improves the linearity and obtains better SNR and SFDR performance. Two switches are added to the pre-stage reference ladder to achieve an accurate measurement of the INL and DNL of the backend ADC, which reduces the calibration complexity and improves the linearity effectively. The method was applied to a 125[Formula: see text]MS/s 14-bit pipeline ADC fabricated in a 0.18[Formula: see text][Formula: see text]m CMOS process. The raw DNL and INL were 1[Formula: see text]LSB and 8[Formula: see text]LSB, respectively, without calibration, but with calibration, they were respectively improved to 0.25[Formula: see text]LSB and 2[Formula: see text]LSB. The ADC achieved an SNR of 64.5[Formula: see text]dB, an SFDR of 73.8[Formula: see text]dB and a THD of 72.7[Formula: see text]dB with a 10[Formula: see text]MHz input signal without calibration, but after calibration these figures were improved to 72.6[Formula: see text]dB, 87.5[Formula: see text]dB and 86.6[Formula: see text]dB, respectively. Its application can also be extended to SAR ADC architecture, etc.

Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation

This paper presents the design of linear ramp generator and digital BIST for an on-chip ADC testing. It replaces the costly and time-consuming traditional mixed signal test methods like DSP-based testing, ATE, etc. The proposed on-chip analog ramp generator uses only a few transistors to generate linear ramp signal. A TIQ comparator based 8-bit flash ADC is taken under test. The output response of the ADC is analyzed in the digital BIST to measure the primary nonidealities affecting the linearity and accuracy of the data conversion. In testing, ADC generates the digital data sequence as a test pattern in response to the ramp input while digital BIST estimates the conversion error. This method does not require DAC and any additional components which increase the area overhead of ADC test. The complete design of ramp generator is integrated with TIQ flash ADC and verified in 0.18[Formula: see text][Formula: see text]m CMOS technology with 1.8[Formula: see text]V of the power supply and 100[Formula: see text]kHz of the input frequency. Measurement of nonidealities shows that the design of an 8-bit flash ADC has good accuracy in data conversion with the differential nonlinearity of [Formula: see text]0.24/[Formula: see text]0.17[Formula: see text]LSB and integral nonlinearity of [Formula: see text]0.44/[Formula: see text]0.04[Formula: see text]LSB.

Energy-efficient and two-step structure switching scheme based on reference-free for SAR ADC

A novel capacitor switching scheme for successive approximation register analogue-to-digital converters is proposed which can achieve a high energy saving, with only two references, Vref and gnd. Due to the two-step architecture is adopted here, the total capacitance is reduced by 48.44% over the conventional structure. Furthermore, based on the most-significant bit capacitor using split-capacitor procedure and monotonic switching method, the proposed switching scheme achieves 99.74% less switching energy over the conventional architecture. Note that during the design procedure, the complexity of logic and auxiliary power supply circuits are further reduced by the lack of the common voltage (Vcm). Besides the significant energy saving in the switching process, the proposed capacitor architecture also has zero consumption in reset energy. Matlab simulation results show the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.644 LSB and 0.825 LSB.

A 10-bit Two-Stage R-DAC With Isolating Source Followers for TFT-LCD and AMOLED Column-Driver ICs

This paper proposes a 10-bit two-stage resistor string digital-to-analog converter (R-DAC) architecture with source followers to isolate parallel-connected resistor strings, with a dc-offset compensation scheme to compensate for the offset voltages of the source followers. To compensate for these offset voltages, another source follower is inserted in the feedback loop of the buffer amplifier. Two prototypes of a 24-channel column driver were fabricated using the 0.18-μm CMOS technology; the worst differential nonlinearity and integral nonlinearity through a one-voltage selection scheme were 0.6 and 0.77 LSB, respectively, and those through a two-voltage selection scheme were 0.4 and 0.52 LSB, respectively. The proposed 10-bit two-stage R-DACs with one-/two-voltage selection schemes occupy only 57%/60% of the area of a conventional 8-bit R-DAC using the same technology.

Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs

This paper presents an on-chip stepwise ramp stimulus generator aimed at static linearity test applications for analog-to-digital converters (ADCs). The proposed ramp stimulus generator is based on a simple switched-capacitor integrator with a constant dc input. The integrator has been conveniently modified to produce a very small integration gain proportional to the capacitance difference of two capacitors, in such a way that the resulting stepwise ramp signal at the output has a step size below the least significant bit (LSB) of the target ADC under test. In order to verify the feasibility of the proposed ramp generation technique, this paper details the design and experimental characterization of a proof-of-concept stepwise ramp generator in a 65-nm CMOS technology. Experimental results on 15 fabricated samples show an average linearity of 14.5 effective bits in a differential output range of ±2 V. Moreover, a discrete-time static linearity measurement strategy is proposed and, as a proof-of-concept validation, it is verified on an off-the-shelf 11-bit ADC using the fabricated generator samples. Experimental results show an accuracy of ±0.3 LSB in the measurement of the integral nonlinearity of the ADC under test.

Compact Analog-To-Digital Converter (ADC) Using Quantum Dot Gate-Quantum Dot Channel Field Effect Transistor (QDG-QDCFET)

The generation of four states in their transfer characteristic of QDG-QDCFET makes them useful to implement four state logic or quaternary logic. On the other hand, the number of device count in a circuit like ADC can also be decreased using this multistate semiconductor device. This work shows the design of a compact analog-to-digital comparator (ADC) where QDG-QDCFET replaces the quantization circuit and reduces the device count. The device-integration increases, which is a major issue for the semiconductor industry. This paper also highlights process variation of the device, different performance parameters and different linearity analysis, such as differential nonlinearity (DNL), integral nonlinearity (INL) of the designed ADC.

A 12bit 250MSPS pipeline ADC with 4 Gbps serial output interface

A 12bit 250MSPS pipeline analog-to-digital converter (ADC) with serial output interface is presented. The pseudo random digital calibration dithered sub-ADC in first stage is used to lower non-ideal errors and improve the dynamic performance in the high speed ADC. An integrated serial output interface is implemented to convert 12bit parallel data into a differential serial data stream. The pipeline ADC was fabricated with CMOS 180 nm 1.8 V 1P5 M process. The active ADC with the serial output interface consumes a power consumption of 395 mW and occupies an area of 8.0 mm2, where the active area of the interface is 0.75 mm2. The measurement results show that the differential non-linearity and integral non-linearity of the proposed ADC are − 0.22/+ 0.16LSB and − 0.4/+ 0.6LSB, respectively. The spurious free dynamic range and signal-to-noise ratio can get 81.17 dB and 69.92 dB with 20 MHz input signal at full sampling speed. The serial output interface provides an eye height greater than 800 mV for data rates of 4 GHz bits per second with a power of 75 mW.

10-Bit Flash ADCs and Beyond: An Automated Framework for TIQ Flash ADCs Design

In this work we introduce the flash ADC design automation (FADA) framework. It aims to reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes the selected TIQ comparators of the flash ADC for differential nonlinearity (DNL), integral nonlinearity (INL), analog voltage range, power consumption and comparator noise values. We performed a survey study on flash ADCs published in the last two decades and compared them to our 10-bit single-channel TIQ flash ADC. Further, it took FADA < 6 h to design the 10-bit TIQ flash ADC compared to few weeks of manual design. Accordingly, FADA selected TIQ comparators set for the 10-bit TIQ flash ADC with DNL and INL values less than 0.17 LSB and 0.16 LSB, respectively, when designed in the ibm65n CMOS technology. The 10-bit TIQ flash ADC has simulated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) values of 57.2 dBs and 61 dBs, respectively. It consumes 1.67 mW of power and operates at 1.57 GSample/s. FADA provides TIQ models to optimize for high-performance versus low-noise TIQ flash ADCs designs.