Integral Nonlinearity Research Articles

A 32 × 32-Pixel CMOS Imager for Quantum Optics With Per-SPAD TDC, 19.48% Fill-Factor in a 44.64-μm Pitch Reaching 1-MHz Observation Rate

This article reports the design and characterization of a 32 $\times $ 32 single-photon avalanche diode (SPAD) time-resolved image sensor for quantum imaging applications fabricated in a 150-nm CMOS standard technology. A per-SPAD time-to-digital converter (TDC) records the spatial cross correlation functions of a flux of entangled photons. Each 44.64- $\mu \text{m}$ pixel with 19.48% fill-factor features a 210.2-ps resolution, 50-ns (8-bit) range TDC with 1.28-LSB differential and 1.92-LSB integral nonlinearity (DNL/INL). The sensor achieves an observation rate of up to 1 MHz through a current-based mechanism that avoids reading empty frames when the photon rates are low. A row-skipping mechanism detects the absence of SPAD activity in a row to increase the duty cycle. These two features require only three transistors in each pixel. The sensor functionality is demonstrated in a quantum imaging experiment that achieves super-resolution.

A Low-Area and Fully Nonlinear 10-Bit Column Driver With Low-Voltage DAC and Switched-Capacitor Amplifier for Active-Matrix Displays

To reduce the circuit area and support a 10-bit fully nonlinear gamma correction, a new column driver architecture constructed with a 10-bit one-stage low-voltage resistor string digital-to-analog converter (RDAC) (LVDAC) and a switched-capacitor amplifier (SC-AMP) is proposed. Because the LVDAC is implemented with low-voltage (LV) MOSFETs instead of high-voltage (HV) MOSFETs, the circuit area is drastically reduced. In addition, there is no need to use level shifters that must be used in the traditional column driver between the LV logic circuit and the HV DAC, thus further decreasing the circuit area. By utilizing a one-stage DAC architecture, the effective bit resolution of nonlinear gamma correction can be increased compared with previous two-stage DACs, in which the output voltages of the coarse DAC are interpolated. The output voltage of LVDAC is amplified by SC-AMP to reach the requisite HV to drive the display panel. In designing the SC-AMP, the effects of non-idealities, such as random offset voltage, capacitance mismatch, parasitic capacitance, and switching error are quantitatively analyzed, and circuit techniques to suppress the effects are presented. The proposed column driver was fabricated using a 90-nm CMOS process. The circuit area of the proposed 10-bit column driver is only 69.0% of that of the conventional 8-bit column driver because the conventional 8-bit HV RDAC (HVDAC) using 5-V MOSFETs is replaced by the proposed 10-bit LVDAC using 1.2-V MOSFETs, along with the SC-AMP with a gain of four to support the 5-V output voltage range. The measurement results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.2/-0.18 and +0.42/-0.06 LSB, respectively, with an LSB voltage of 4.5 mV. The measured maximum deviation of voltage outputs (DVOs) between 50 channels is 7.9 mV.

A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration

We discuss a 12-b 18-GS/s analog-to-digital converter (ADC) implemented in 16-nm FinFET process. The ADC is composed of an integrated high-speed track-and-hold amplifier (THA) driving up to eight interleaved pipeline ADCs that employ open-loop inter-stage amplifiers. Up to 10 GS/s, the THA operates at the full sampling rate using a non-interleaved single sample network, thereby eliminating the interleaving sampling time and bandwidth mismatch. Above 10 GS/s, the THA is programmed to use two ping-ponged, or an optional (2 + 1) randomized, sample networks to spread the residual post-calibration interleaving spurs in the noise floor. The THA enables an input bandwidth of 18 GHz and employs dither injection and optional pseudorandom chopping. In the pipeline stages, dither-based background calibration detects and corrects gain, settling, memory, and kick-back errors. New dither-based background calibration algorithms are employed to detect and correct the arbitrary non-linearity in the form of integral non-linearity (INL) breaks and harmonic distortion up to the fifth order in the THA and in the references, DACs, and inter-stage open-loop amplifiers of the pipeline ADCs. Moreover, new dither-based background calibration is implemented to detect and correct the chopping non-idealities, memory errors, interleaving mismatches, and order-dependent randomization errors. Compared to the fastest state-of-the-art with similar performance, this ADC achieves 80% higher sample rate and 2.4× higher input bandwidth, and incorporates a THA that supports a 3.3× higher non-interleaved sample rate.

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

PurposeThe purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application.Design/methodology/approachAn op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2.FindingsMeasured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V.Originality/valueThe experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

LTARS: analog readout front-end ASIC for versatile TPC-applications

We designed a versatile analog front-end chip, called LTARS, for TPC-applications, primarily targeted at dual-phase liquid Ar-TPCs for neutrino experiments and negative-ion μ-TPCs for directional dark matter searches. Low-noise performance and wide dynamic range are two requirements for reading out the signals induced on the TPC readout channels. One of the development objectives is to establish the analog processing circuits under low temperature operation, which are designed on function block basis as reusable IPs (Intellectual Properties). The newly developed ASIC was implemented in the Silterra 180 nm CMOS technology and has 16 readout channels. We carried out the performance test at room temperature and the results showed an equivalent noise charge of 2695±71 e− (rms) with a detector capacitance of 300 pF. The dynamic range was measured to be 20–100 fC in the low-gain mode and 200–1600 fC in the high-gain mode within 10% integral nonlinearity at room temperature. We also tested the performance at the liquid-Ar temperature and found a deterioration of the noise level with a longer shaper time. Based on these results, we also discuss a unique simulation methodology for future cold-electronics development. This method can be applicable to design the electronics used at low temperature.

Precision measurement of ADC parameters with cumulative histogram technique using Gaussian noise

Analog to Digital Converter (ADC) is a significant part of any electronic measurement and instrumentation system. It affects the overall accuracy of the system, therefore it should be characterized and tested precisely. The ADC testing methods, available in literature use deterministic signals as stimuli and have certain limitations. This paper presents statistical testing of ADC based on the cumulative histogram technique with white Gaussian noise as stimuli. The proposed method is not much more explored in literature and shows improvement in the estimation of parameters. A large number of samples of Gaussian noise is simulated and applied to the simulated 5–10 bit ADC. The cumulative histogram is estimated, and the code transition level is calculated to obtain the transfer characteristics of ADC. The linear regression method is employed on the transfer characteristics and the best-fit line is obtained. Corrections have been applied to nullify the gain and offset error. Comparative analysis of the transfer characteristics of simulated ideal and actual ADC will lead to develop the algorithm for the estimation of static parameters Gain, offset, Integral and Differential nonlinearities, and the Effective Number of Bits. The analytical expression for the precision measurement of these parameters is derived. Simulation results are presented in support of the derived expression of the proposed method. Obtained results are compared with the results presented in the literature and hence the effectiveness of the method.

Ultra-Low Power CMOS Image Sensor With Two-Step Logical Shift Algorithm-Based Correlated Double Sampling Scheme

This article presents an ultra-low power counter structure for a column-parallel single-slope analog-to-digital converter (SS-ADC) in CMOS image sensors. The proposed counter employs a two-step logical shift algorithm-based correlated double sampling (CDS) scheme. The logical shift algorithm can reduce parasitic capacitances, driving frequency, and inner toggling nodes by using the minimum number of transistors and a single-direction counter structure. Moreover, the two-step counting and double data rate scheme in the LSB counter can halve the operating clock frequency, resulting in further decreased power consumption. A prototype sensor was fabricated using a 110 nm CMOS image sensor process. The measurement results show that the proposed SS-ADC with a two-step counter consumes 2.4 μW power per column and shows a differential nonlinearity of +0.38/-0.25 LSB and an integral nonlinearity of +0.75/-0.5 LSB. The total power consumption is 2.25 mW for 640 × 480 effective image resolution at 60 frame rates with 3.3 V/1.5 V supply voltage.

An Opamp-Less PVT Compensation Structure for Ramp Generator Circuit

Accurate ramp signal, with low power dissipation, is highly demanded, for applications like counter ADC. This paper presents a novel low power ramp generator circuit with a negative feedback loop for compensation of the variations in process, voltage, and temperature (PVT). While using an opamp for PVT compensation has been essential in the previous ramp generator structures, the proposed ramp generator is opamp-less. Derived equations of the proposed ramp generator circuit show that PVT compensation structure works effectively. In addition, the circuit design and simulations were done in TSMC 0.18[Formula: see text][Formula: see text]m CMOS technology. Corner analysis shows that integral non-linearity (INL) of the ramp signal is about 3.7[Formula: see text]mV, for a wide temperature range, while the power dissipation of the circuit is about 1.16[Formula: see text][Formula: see text]W.

Design and Calibration Techniques for a Multichannel FPGA-Based Time-to-Digital Converter in an Object Positioning System

A multichannel field-programmable gate array (FPGA)-based time-to-digital converter (TDC) and its calibration techniques are presented. Herein, a frequency-tracker-based sliding-scale technique and a moving-average filter to improve the linearity and resolution are proposed. The error calibration technique automatically detects and corrects conversion errors caused by variations and mismatches in the propagation delays. The gain calibration extracts the average bin width of the fine TDC and resolves any linearity degradation in the coarse/fine interpolation architecture. The proposed techniques were applied to a four-channel TDC design implemented on a Xilinx Artix-7 FPGA. The measured differential and integral nonlinearities of all channels were within 0.51 least significant bit of 4.88 ps. The root-mean-squared resolution of the output code was 2.90–8.03 ps across a wide input range of 350 $\mu \text{s}$ .

A fully integrated 10-bit 100 MS/s SAR ADC with metastability elimination for the high energy physics experiments

This paper presents a fully integrated 10-bit 100 MS/s successive approximation register (SAR) ADC for the high energy physics experiments. The ADC uses a non-binary weighted capacitor digital-to-analog converter (C-DAC) network and a hybrid capacitor switching procedure to increase conversion accuracy and speed. A metastability elimination technique is employed to avoid comparator metastability, and then reduce the conversion error rate (CER) at high-speed asynchronous operations. The full custom static logic is used to improve the radiation hardness. The ADC was designed and fabricated in a 40 nm CMOS process. It occupies 0.078 mm2 active area, including a reference generator, with a core area of 0.037 mm2. The measured ADC core power consumption and the total power consumption are 1.32 mW and 8.5 mW respectively, including the reference generator at a 1.1 V supply. The resulting figure-of-merit (FOM), for sampling rate 100 MS/s, is 130 fJ/conversion-step. It achieves a good dynamic performance with ∼9.3-bit effective number of bits (ENOB) at 100 MS/s with 14.97 MHz input signal. The measured spurious free dynamic range (SFDR), total harmonic distortion (THD) and signal-to-noise ratio (SNR) are 72.6 dB, −69.2 dB, 58.3 dB, respectively. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.62/−0.4 LSB and +0.67/−0.54 LSB respectively.

All-Digital CMOS Time-to-Digital Converter With Temperature-Measuring Capability

This brief presents an all-digital CMOS pulse-shrinking time-to-digital converter (TDC) with temperature-measuring capability for higher circuit value and cost saving. A pulse generator is proposed to generate either a time-added pulse or a temperature-sensing pulse. A cyclic delay line (DL) composed of a temperature-sensing DL and a pulse-shrinking DL becomes area efficient and achieves sufficiently wide dynamic range. A time subtractor that eliminates the effect of the offset error enhances accuracy. The proposed TDC is fabricated with TSMC 0.35- $\mu \text{m}$ CMOS process and has a small area of approximately 0.019 mm2. The effective time resolution is approximately 45 ps, with an integral nonlinearity of −0.5 to 0.85 least significant bit (LSB). The achieved temperature resolution is nearly 0.1 °C/LSB, with an inaccuracy of −1.35 °C to 0.7 °C for a range of 0 °C–90 °C. Experimental results prove that we have proposed the first TDC that successfully measures time and temperature.

New digital background calibration method for pipelined ADCs

Purpose Pipelined analog-to-digital converters (ADCs) are widely used in electronic circuits. The purpose of this paper is to propose a new digital background calibration method to correct the capacitor mismatch, finite direct current (DC) gain and nonlinearity of residue amplifiers in pipelined ADCs. Design/methodology/approach The errors are corrected by defining new functions based on generalized Newton–Raphson algorithm. Although the functions have analytical solutions, an iterative procedure is used for calibration. To accelerate the calibration process, proper initialization for the errors is identified by using evaluation estimation block and solving inverse matrix. Findings Several behavioral simulations of a 12-bit 100MS/s pipelined ADC in MATLAB indicate that signal-to-(noise + distortion) ratio (SNDR) and spurious free dynamic range (SFDR) are improved from 30dB/33dB to 70dB/79dB after calibration. Calibration is achieved in approximately 2,000 clock cycles. Practical implications The digital part of the proposed method is implemented on field-programmable gate array to validate the performance of the pipelined ADC. The experimental result shows that the degradation of SNDR, SFDR, integral nonlinearity, differential nonlinearity and effective number of bits is negligible according to fixed-point operation vs floating-point in simulation results. Originality/value The novelty of this study is to use Newton–Raphson algorithm combined with appropriate initialization to reduce the number of divisions as well as calibration time, which is suitable in the recent nano-meter complementary metal oxide semiconductor technologies.

Accurate exponential histogram test method for ADC linearity test

An accurate exponential histogram test (EHT) method is proposed for the ADC linearity test. Different from conventional EHT methods which estimate ADC static parameters only based on the number of hits, the proposed method accurately estimates the ADC transition levels, differential non-linearity and integral non-linearity by creative utilisation of the information of stimulus signal. As a result, the proposed method avoids the errors introduced by the assumed proportional relationship between the code width and the number of hits in conventional methods. Simulation results show that the proposed method outperforms the conventional methods in terms of accuracy and robustness.

A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique

In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of $$568\,\upmu \hbox {m} \times 298\,\upmu \hbox {m}$$ and consumes a power as less as $$0.28\,\upmu \hbox {W}$$ . It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/− 0.84 least significant bit (LSB) and + 0.1/− 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step.

Median Selection for Calibrating the Capacitor Mismatch to Improve the Linearity of Analog-to-Digital Converter

This paper presents a capacitor calibration technique called median selection for improving the static and dynamic performance of the successive approximation register (SAR) analog-to-digital converter (ADC). Monte Carlo simulations in MATLAB are presented to demonstrate the effect of the proposed method. Simulation results show that for an 18-bit RC-hybrid SAR ADC with the mismatch of the unit capacitor ( $${\sigma _u} = {{{\sigma _0}}\big / {{C_u}}}$$ ) of 0.05%, the root mean square (rms) of differential nonlinearity is improved by 94.7%–0.23 LSB and the rms of integral nonlinearity is promoted by 96.7%–0.20 LSB by the proposed median selection. On the other hand, the median selection improves the mean value of the spurious free dynamic range from 94.09 to 128.85 dB, while the mean value of the signal-to-noise-and-distortion ratio is improved from 88.70 to 109.82 dB.

Design and Characterizations of the Radiation-Hardened XCR4C ASIC for X-Ray CCDs for Space Astronomical Applications

Correlated double sampling (CDS) circuits are essential to processing the X-ray charge-coupled devices (CCDs) that have been widely used in the modern X-ray astronomical field. For timing observations, both energy resolution and timing resolution are of great importance. We are developing the XCR4C application-specific integrated circuit (ASIC), which is a fully customized four-channel radiation-hardened CDS ASIC targeting the readout of X-ray CCDs, for future space astronomical missions. The ASIC is implemented in a differential switched-capacitor architecture, making it highly linear, low power, immune to common-mode noise and interferences, as well as easily configurable. To combat the harsh low-earth-orbit space environment, some radiation-hardening techniques are applied, including the process hardening method, even-finger double-side bulk butting, and pseudo-double guard ring layout techniques. The XCR4C ASIC was fabricated with 0.35- $\mu \text{m}$ 2P4M CMOS technology with an epitaxial layer. The ASIC achieves a maximum 23-ppm integral nonlinearity and 5.8 e− rms equivalent noise charge under a typical 1-MHz pixel rate and only consumes 50 mW approximately from a single 3.3-V supply voltage. The results from radiation hardness assurance testing show that the ASIC has at least a total ionizing dose tolerance of 300 krad(Si), and no single-event latchup has been found up to a linear energy transfer of $81.35~\text {MeV}\cdot \text {cm}^{2}$ /mg with a total fluence up to $1.68\times 10^{7}$ ions/cm2.

A Low-Power Column-Parallel Gain-Adaptive Single-Slope ADC for CMOS Image Sensors

A low-power column-parallel gain-adaptive single-slope analog-to-digital converter (ADC) for CMOS image sensors is proposed. The gain-adaptive function is realized with the proposed switched-capacitor based gain control structure in which only minor changes from the traditional single-slope ADC are required. A switched-capacitor controlled dynamic bias comparator and a flip-reduced up/down double-data-rate (DDR) counter are proposed to reduce the power consumption of the column circuits. A 12-bit current steering digital-to-analog converter (DAC) with a two-dimensional gradient error tolerant switching scheme is adopted in the ramp generator to improve the linearity of the ADC. The proposed techniques were experimentally verified in a prototype chip fabricated in the TSMC 180 nm CMOS process. A single-column ADC consumes a total power of 63.2 μ W and occupies an area of 4.48 μ m × 310 μ m. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are −0.43/+0.46 least significant bit (LSB) and −0.84/+1.95 LSB. A 13-bit linear output is acquired in nonlinearity within 0.08% of the full scale after calibration.

Design of 1Gsps high-speed data acquisition card

In order to digitize the High-Frequency signal, a 12-bit 1Gsps RF Sampling data acquisition system is designed. The digital acquisition system includes an Analog-to-Digital Converter (ADC) daughter card and a data processing mother card equipped with Field Programmable Gate Arrays (FPGA) for communication, which has an external DDR3 memory module and a Gigabit Ethernet Interface. It focuses on the hardware system implementation of the daughter card and the realization of data receiving, transferring, and sending based on the FPGA. The test results show that the Effective Number of Bit (ENOB) of the acquisition card is above 9.1 Bits. Both Integral Non-Linear (INL) and Differential Non-Linearity (DNL) are anticipated. It accomplishes the requirements for engineering applications in many fields excellently.

9 ps TDC based on multiple sampling in 0.18 μm complementary metal–oxide–semiconductor

A high-precision measurement method, based on multiple sampling, is proposed for the time interval of two signals in this study. A time interval measurement circuit integrated into the time-to-digital converter (TDC), is designed based on this high-precision measurement method. In the TDC, the authors use two identical delay lines as the holding module to ensure the two signals with a constant time interval. The TDC samples the two signals multiple times by a clock signal, whose period is shorter than that of the delay line. Consequently, the problem of limited resolution caused by a mismatch between delay lines in the delay-line structure can be avoided, and the precision of the output can be improved. The proposed TDC is designed and simulated in Semiconductor Manufacturing International Corporation (SMIC) 0.18 μm complementary metal-oxide-semiconductor process. Simulation results show that the differential non-linearity and the integral non-linearity are always less than one least significant bits. The proposed TDC achieves input dynamic range of 0-32.13 ns and time resolution of 9 ps.

A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors

This brief proposes a successive approximation register (SAR) analog-to-digital converter (ADC) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC's linearity of 10 bit within a 5 bit accuracy's settling time. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC. Measurement results of 15 columns of SAR ADCs, sampling at 5 MS/s on the same CMOS image sensor (CIS) chip, show integral nonlinearity (INL) around 3 LSB (1LSB = 1 mV), when sampling at 5 MHz, after a proposed swift digital background calibration that incurs no additional hardware complexity. The CIS array read out by the proposed column-level SAR ADCs is measured reasonable photoelectron transfer characteristics.