Integral Nonlinearity Research Articles

ADC Nonlinearity Correction for the Majorana Demonstrator

Imperfections in analog-to-digital conversion (ADC) cannot be ignored when signal digitization requirements demand both wide dynamic range and high resolution, as is the case for the Majorana Demonstrator <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">76</sup> Ge neutrinoless double-beta decay search. Enabling the experiment's high-resolution spectral analysis and efficient pulse shape discrimination required careful measurement and correction of ADC nonlinearities. A simple measurement protocol was developed that did not require sophisticated equipment or lengthy data-taking campaigns. A slope-dependent hysteresis was observed and characterized. A correction applied to digitized waveforms prior to signal processing reduced the differential and integral nonlinearities by an order of magnitude, eliminating these as dominant contributions to the systematic energy uncertainty at the double-beta decay Q value.

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters

An extremely high-resolution, 2-D Vernier field-programmable gate array (FPGA) time-to-digital converter (TDC) with phase wrapping and averaging has been proposed recently to get an extremely fine resolution of 2.5 ps. However, the cell delays in a delay matrix are not fully controlled so that the TDC performance strongly depends on the stochastic distribution of cell delays, and the input range is limited to less than 20 ns. To achieve both high-precision phase division and wide measurement range, a phase-locked loop (PLL)-based delay matrix, which is capable of overclocking and double data rate (DDR), is proposed in this article. All delay cells are under the precise control of PLLs to generate output phases evenly divided within the reference clock period. For a concept proof, the TDC architecture is implemented on an Altera Stratix-IV FPGA chip to achieve 15.6-ps resolution. The differential nonlinearity (DNL), integral nonlinearity (INL), and rms resolution are measured to be merely −0.157 to 0.137 LSB, −0.176 to 0.184 LSB, and 1.0 LSB, which prove the superiority of the proposed structure to its stochastic counterparts. The proposed high-precision phase division technique can be applied to not only the TDC but also the digital-to-time converter (DTC) to enrich its future applications.

A CMOS image sensor with a 10 ​MHz column readout speed using digitally calibrated pipelined ADCs

This paper presents a proof-of-concept CMOS image sensor (CIS) having a continuous column readout speed of 10 ​MHz. Each column readout chain, from the pixel output to the chip digital outputs, is composed of two cascade programmable gain amplifiers (PGAs) and a 10 bit 1.5 bit/stage pipelined ADC, all operating at 10 ​M samples per second. A digital background calibration method is proposed to remove the nonlinearity resulted from the capacitor mismatches in the multiplying DACs (MDACs) in each pipelined ADC stage. Measurement results from 16 columns of 10 bit single-ended pipelined ADCs show Integral Nonlinearity (INL) around 4 LSB and an Effective Number Of Bits (ENOB) of 8 (reference voltage of 1 Vpp), after being digitally calibrated. Compared to the state-of-the-art column ADCs for high speed CISs, this design has a higher speed with a figure-of-merit (FOM) of 3.2 pJ/conv. The proposed CIS’s measured photoelectron transfer characteristics is shown at a column readout rate of 10 ​MHz.

Photonic digital-to-analog conversion using a blue frequency chirp in a semiconductor optical amplifier.

In this Letter, we present a photonic digital-to-analog conversion (DAC) technique based on blue-chirp spectral slicing using a semiconductor optical amplifier (SOA). Because the gain change in an SOA leads to a refractive-index change based on the change in intensity of the input data signal, the probe signals experience a dynamic frequency shift to a shorter-wavelength side called a blue-chirp. After passing through the SOA, the probe signals corresponding to the logic level of the input digital signal are extracted by filtering only the blue-chirp component of the probe signals using rectangular-shape filters. In this study, we experimentally demonstrate a 10-Gb/s, 2-bit photonic DAC from a 10-Gb/s digital signal with various data patterns to a four-level amplitude signal assuming an analog signal. In addition, we evaluate the resolution performance of the photonic DAC in terms of differential and integral nonlinearities and an effective number of bits.

A 99.43% Energy Saving Switching Scheme with Asymmetric Binary Search Algorithm for SAR ADCs

In this paper, a low-energy switching scheme based on the asymmetric binary search algorithm for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. To reduce switching energy and area, the proposed scheme uses the single-side switching method and the least significant bit (LSB) capacitor is split into two one-half unit capacitors. Using the series capacitance scheme, the capacitance mismatch caused by process deviation is effectively improved. Compared with the conventional switching method, the switching energy of this scheme is decreased by 99.43% and the area is saved by 87.2%. MATLAB simulation results show that this scheme also has a low nonlinearity that the maximum differential nonlinearity is only 0.37 LSB and the maximum integral nonlinearity is only 0.43 LSB.

A low‐power, low‐data‐rate efficient ADC with hybrid exponential‐linear transfer curve for bio‐potential recording systems

SummaryA digital‐ramp hybrid exponential‐linear analog‐to‐digital converter (ADC) is presented in this paper, which is attractive, where a high dynamic range (DR) is required. It is especially applicable for sampling neural (bio‐potential) signals, as most of the neural signal data are concentrated on higher side of the amplitude range. By the exponential quantization function for low signal amplitudes, the background noise that disperses in lower amplitudes will be reduced. For higher signal amplitudes, the exponential function optionally switches to linear function at an adjustable voltage threshold, to reduce required number of bits for those high amplitudes, as well. As a result of this exponential‐linear hybrid operation, the total data rate and the power required for data transmission are decreased. A prototype 8‐bit counter‐based exponential ADC is designed and simulated in 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS). The 20‐KS/s ADC achieves a DR of 66 dB, occupies 0.036 mm2 area, and consumes 6.4‐μW power from a 1.8‐V supply. Integral nonlinearity (INL) and differential nonlinearity (DNL) that are redefined to be compatible with nonlinear ADCs are 3.2 and 0.88 least significant bits (LSBs), respectively.

Different Analog to Digital Converters Architectures

A series of recent studies has indicated that a mixed signal device analog to digital converters used for the processing of information and play a vital role in wireless sensors, Digital signal processing, Biomedical devices, in communication, IOT and various other applications. Across this broad use they give the significance in designing. The paper represents the various parameters like speed, area occupied, power consumption, sampling Rate, precision, Signal to noise ratio, Signal to noise distortion ratio, resolution, linearity and conversion time with respect to its different types and broad application in the real world. It defines errors due to non – linearity of signals as Differential nonlinearity, Integral nonlinearity, gain error, quantization error, aliasing and offset error. It also gives the comparative study about ADCs.

A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology

A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog converters, and the eight least significant bits are determined by a two-channel time-interleaved successive-approximation-register (TI-SAR) quantizer. An integrated input buffer and an operational amplifier with improved voltage efficiency at 1.8 V are adopted to achieve high-linearity stably in wide band for 1 GS/s. By designing a 500 MS/s 8-bit SAR quantizer at 1 V, the number of required interleaved channels is minimized to simplify the complexity and an adaptive power/ground is used to compensate the common-mode mismatch between the blocks in different power supply voltages. The offset and gain mismatches due to the TI-SAR quantizer are compensated by a calibration scheme based on virtually-interleaved channels. This ADC is fabricated in a 40 nm complementary metal-oxide-semiconductor (CMOS) technology, and it achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.2 dB and a spurious free dynamic range (SFDR) of 72 dB with a 69 MHz input tone. When the input frequency increases to 1814 MHz in the fourth Nyquist zone, it can maintain an SNDR of 55.3 dB and an SFDR of 64 dB. The differential and integral nonlinearities are −0.94/+0.85 least significant bit (LSB) and −3.4/+3.9 LSB, respectively. The core ADC consumes 94 mW, occupies an active area of 0.47 mm × 0.25 mm. The Walden figure of merit reaches 0.14 pJ/step with a Nyquist input.

12 b 50 MS/s 0.18 μm CMOS SAR ADC based on highly linear C‐R hybrid DAC

A 12 b 50 MS/s successive-approximation register (SAR) ADC with a highly linear C-R hybrid DAC is presented. The proposed DAC significantly reduces the required total number of unit capacitors by processing the upper bits based on a binary-weighted capacitor array and the remaining lower bits based on reference segment voltages, which are obtained from a simple resistor string. The reduced number of unit capacitors enables the use of larger unit capacitance, resulting in improved matching accuracy. In the C-R hybrid DAC, an input range scaling technique, which matches a full-scale input range to the reference voltage range, implements the binary-weighted SAR operation without additional capacitors and reference voltages. The DAC linearity is improved considerably through the process-insensitive capacitor-array layout, which cancels out oxide-gradient errors. The prototype ADC in a 0.18 μm CMOS process demonstrates measured differential and integral non-linearities within 0.71 LSB and 0.85 LSB at 12 b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 64.3 and 74.7 dB at 50 MS/s, respectively. The ADC occupies an active die area of 0.17 mm2 and consumes 2.63 mA with a 1.8 V supply voltage.

An Area-Efficient 10-Bit Buffer-Reused DAC for AMOLED Column Driver ICs

In this paper, we proposed an area-efficient 10-bit digital-to-analog converter (DAC) with buffer-reusing method to dramatically relief the severe area exploding issue in high-definition active-matrix organic light-emitting diode (AMOLED) driver integrated circuits (ICs). In our design, we implement the functionalities of a large number of switches and capacitors in conventional DAC by a compact internal buffer. Furthermore, we minimize the buffer capacity requirement by elaborately reusing the indispensable output buffer in the typical column driver. In this way, we can cut down nearly a half of the decoder-switches and simultaneously reduce the capacitor size from 8 C to 3 C without designing an intricate and power-consuming amplifier separately. A prototype 6-channel column driver employing the proposed buffer-reused DAC was fabricated by 0.35 μm 2P3M BCD (Bipolar, CMOS, DMOS) process and its effective layout area per channel is 0.0429 mm2, which is 42.8% smaller than that of the conventional 10-bit R-C DAC. Besides, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.514 LSB/0.631 LSB, respectively and the maximum value of inter-channel deviation voltage output (DVO) is 3.25 mV. The settling time within 5.6 μs is readily achieved under 1.5 kΩ-resistance and 100 pF-capacitance load. Measurement results indicate that the proposed buffer-reused DAC can successfully minimize the die area while maintaining other required performances.

A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC

An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent large feedback factor (ideally β = 1) of the proposed FADAC, enables a power-efficient low-voltage high-resolution pipelined ADC design. The 1-bit FADAC is exploited in a SHA-less and opamp-sharing pipelined ADC, exhibiting 12-bit resolution with an input swing of 1.8 Vpp under a 1.1 V power supply. Fabricated in a 0.13-μm CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling rate. The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm2. The measured differential nonlinearity (DNL) is +0.72/−0.52 least significant bit (LSB) and integral nonlinearity (INL) is +0.84/−0.75 LSB at a 3-MHz sinusoidal input.

Reshuffled Diagonal Rotated Walk Switching Scheme for DAC INL Reduction

This brief proposes a new switching scheme without division of weighting elements into several parts for unary digital-to-analog converters. The switching scheme is universal, i.e., it can be applied to a unary array with an even resolution of 4 bits and higher. A comparison of universal switching schemes showed that the proposed switching scheme reduces the maximum integral nonlinearity by 12–44% relative to the best-known one, the $\text{Q}^{N}$ Rotated Walk. Moreover, the proposed switching scheme gives an improvement of up to 50% in a comparison with non-universal switching schemes.

A 0.3V 10b 3MS/s SAR ADC With Comparator Calibration and Kickback Noise Reduction for Biomedical Applications.

This paper presents a 10-bit successive approximation analog-to-digital converter (ADC) that operates at an ultralow voltage of 0.3 V and can be applied to biomedical implants. The study proposes several techniques to improve the ADC performance. A pipeline comparator was utilized to maintain the advantages of dynamic comparators and reduce the kickback noise. Weight biasing calibration was used to correct the offset voltage without degrading the operating speed of the comparator. The incorporation of a unity-gain buffer improved the bootstrap switch leakage problem during the hold period and reduced the effect of parasitic capacitances on the digital-to-analog converter. The chip was fabricated using 90-nm CMOS technology. The data measured at a supply voltage of 0.3 V and sampling rate of 3 MSps for differential nonlinearity and integral nonlinearity were +0.83/-0.54 and +0.84/-0.89, respectively, and the signal-to-noise plus distortion ratio and effective number of bits were 56.42 dB and 9.08 b, respectively. The measured total power consumption was 6.6 μW at a figure of merit of 4.065 fJ/conv.-step.

Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5 + 5 + 6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a $0.6~\mu m$ standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm $\times6.6$ mm. As for single channel SAR ADC, the area is 0.9mm $\times2.0$ mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output offset storage (OOS) technique, a new correlated double sampling (CDS) is adopted to reduce the non-uniformity in column-level ADCs. In the proposed structure, the decision point of the comparator is independent of the input signal. The variation of the comparator offset caused by the input level is eliminated. Through a foreground calibration, the non-idealities from the ramp generator and the column ADC are both corrected. Design and simulation in a 130nm CMOS process, the proposed ADC achieves the differential nonlinearity (DNL) of +0.76/−0.8 LSB and the integral nonlinearity (INL) of +1.06/−0.84 LSB at a sampling frequency of 100 KS/s with the calibration. The effective number of bits (ENOB) is also improved from 4.66 bits to 11.25 bits. The single ADC occupies an active area of $7.5\times 775\,\,\mu \text{m}^{2}$ and the power consumption is $72~\mu \text{W}$ .

A 10‐bit 500‐MS/s Current Steering DAC with Improved Random Layout

According to the segmented current steering Digital-to-analog converter (DAC), the influence of current mismatch and output impedance of the current array on the linearity of DAC is discussed by theoretical analysis and derivation. An optimized layout plan for the current source array randomizes all these unit current sources corresponding to each thermometer code, which can significantly reduce the fist-order and second-order systematic mismatch errors in the current source array, and improve the linearity performance of DAC. With the segmented structure of 6 bit thermometer code and 4 bit binary code, a 10-bit DAC is realized in a 0.18mm CMOS by using the above layout plan. The active area of this DAC is 620μm × 340μm. Operated at 1V digital supply and 1.8V analog supply, with 500 MS/s sampling rate, the measured power consumption of this DAC is 14.3mW. The measurement results show that the Differential nonlinearity (DNL) and the Integral nonlinearity (INL) of the DAC with this random layout scheme are 0.71 LSB and 1.02 LSB. With 500 MS/s sampling rate and 1.465MHz input frequency, the Spurious free dynamic range (SFDR) and the Effective number of bits (ENOB) are 65.6dB and 9.2 bit, respectively.

A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme

This paper presents a 10-bits successive approximation register analog-to-digital converter (SAR ADC) for low-power applications. The input signals are multiplied by two because the dual sampling technique is used during the sampling phase. In this design, a comparator circuit with four input terminals was also applied to implement a fully differential capacitive digital-to-analog converter (CDAC). Simultaneously, by employing an area-efficient and low-energy switching scheme for the capacitive digital-to-analog converter, the average switching energy can be reduced significantly. The proposed design also achieved a reduction in the number of the capacitors and the controlled switches compared with those required in the conventional SAR ADC design. A prototype had been designed and implemented using TSMC 90-nm CMOS 1P9M technology. The measurement results showed that differential nonlinearity and integral nonlinearity of 0.36 least significant bit (LSB) and 0.45 LSB, respectively. At a sampling rate of 50-MS/s with a single 1.2-V power supply, the power consumption was $664~\mu \text{W}$ . This design also achieved a signal-to-noise-and-distortion ratio of 57.6 dB and spurious-free dynamic range of 65.8 dB at the input frequency of 5-MHz. The ADC core occupied an active area of $102\times 235\,\,\mu \text{m}^{2}$ .

A Low-power Extended-counting Delta-sigma ADC for CMOS Image Sensors

This paper presents an incremental delta sigma analog to digital converter (ADC) using an extended counting technique for CMOS image sensors. A modified extended counting method is proposed to reduce the over sampling ratio (OSR) and consequently increase conversion speed without increasing the hardware complexity. To further reduce the chip size and power consumption, a self-biased amplifier is shared between the adjacent stages of the delta-sigma modulator. The proposed ADC is fabricated in a 0.18-㎛ CMOS image sensor process and occupies 0.0026 ㎟. It achieves 65 ㏈ of signal noise and distortion ratio (SNDR) for a signal bandwidth of 156.25 ㎑ with a 20 ㎒ operating clock and consumes 45 μW from a 1.8 V power supply. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49 / −0.22 and +0.61 / −0.64 LSB (least significant byte), respectively.

A Fast Settling Fractional-$N$ DPLL With Loop-Order Switching

The enhancement in the settling response of frequency synthesizers would open up prospects for new applications such as spread spectra and frequency hopping systems. Toward deriving a methodology for a fast settling response, we present a switched-loop digital phase locked loop (DPLL) incorporating an integral-derivative controller-based subsystem. The dominant features accelerating the settling response with low jitters in this DPLL are: 1) hybrid phase detection with a state machine using differential and double integration filtering effect and 2) a time-interleaved direct digital synthesizer (DDS)-based digital-to-time converter (DTC) with stable-edge sampling. A 5-GHz fractional- $N$ DPLL (FNDPLL) has been implemented in CMOS 65-nm-LL technology with the proposed technique of loop-order switching. The measured results of the implemented FNDPLL highlight that the system is capable of fastest reported frequency settling to ±25-ppm error within 1.5 ${\mu }\text{s}$ , using a reference clock frequency of 100 MHz. With one-time calibration, the downsampled output of DDS array-based phase interpolator achieves an integral nonlinearity (INL) of 0.25 ps, as a fractional divider in the loop.