Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation

Abstract

This paper presents the design of linear ramp generator and digital BIST for an on-chip ADC testing. It replaces the costly and time-consuming traditional mixed signal test methods like DSP-based testing, ATE, etc. The proposed on-chip analog ramp generator uses only a few transistors to generate linear ramp signal. A TIQ comparator based 8-bit flash ADC is taken under test. The output response of the ADC is analyzed in the digital BIST to measure the primary nonidealities affecting the linearity and accuracy of the data conversion. In testing, ADC generates the digital data sequence as a test pattern in response to the ramp input while digital BIST estimates the conversion error. This method does not require DAC and any additional components which increase the area overhead of ADC test. The complete design of ramp generator is integrated with TIQ flash ADC and verified in 0.18[Formula: see text][Formula: see text]m CMOS technology with 1.8[Formula: see text]V of the power supply and 100[Formula: see text]kHz of the input frequency. Measurement of nonidealities shows that the design of an 8-bit flash ADC has good accuracy in data conversion with the differential nonlinearity of [Formula: see text]0.24/[Formula: see text]0.17[Formula: see text]LSB and integral nonlinearity of [Formula: see text]0.44/[Formula: see text]0.04[Formula: see text]LSB.