Input Matching Network Research Articles

Design and fabrication of a GaN HEMT power amplifier based on hidden Markov model for wireless applications.

Improvement of power amplifier's performance is the desired topic in communication systems. There are many efforts are made to provide good input and output matching, high efficiency, sufficient power gain and appropriate output power. This paper presents a power amplifier with optimized input and output matching networks. In the proposed approach, a new structure of the Hidden Markov Model with 20 hidden states is used for modeling the power amplifier. The widths and lengths of the microstrip lines in the input and output matching networks are defined as the parameters that the Hidden Markov Model should optimize. For validating our algorithm, a power amplifier has been realized based on a 10W GaN HEMT with part number CG2H40010F from the Cree corporation. Measurement results have shown a PAE higher than 50%, a Gain of about 14 dB, and input and output return losses lower than -10 dB over the frequency range of 1.8-2.5 GHz. The proposed PA can be used in wireless applications such as radar systems.

넓은 입력전력 범위를 갖는 S-대역 광대역 고조파 응답기

This paper presents a through-type harmonic transponder for S-band nonlinear radar. To increase the operating frequency range, a 2-stage L-shaped matching network was configured for the input and output matching networks. In previous studies, conventional harmonic transponders were configured with λ/4 stubs in the input and output matching networks to minimize the influence of these networks because the impedance mismatch suppresses the second harmonic and fundamental signals. However, in this design, a λ/4 open stub was utilized at the output and configured with the output matching network to alleviate the insertion loss of the additional open stub. For verification, the proposed circuit was implemented with the circuit size of 37.6 mm×16.1 mm. The measurement results show that the conversion gain is maintained over −15 dB for frequencies between 2.8~3.8 GHz at −5.5 dBm and −17.5~11 dBm at 3.1 GHz of input power.

Design of a broadband GaN 12 W power amplifier

AbstractA compact broadband 12 W power amplifier with broadband matching networks is presented. Transistors connected in parallel are used to synthesize the high power. Input, interstage, and output matching networks are also properly designed to meet the requirement of the broadband application. The broadband high power amplifier (HPA) was fabricated using a 0.15‐μm gallium nitride (GaN) HEMT technology, with a maximum saturated measured output power of 43 dBm from 6 to 18 GHz. The measured power added efficiency exceeds 20% in the whole interested band. The proposed HPA also has a compact size of 3.1 mm × 2.96 mm.

A 2–10-GHz Reconfigurable GaN Power Amplifier With Average Power-Added Efficiency of 30% and Output Power of 2 W

In this brief, a 2–10 GHz reconfigurable power amplifier (PA) with power-added efficiency (PAE) of 30% and output power of 2W is proposed using commercial <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.25~\mathbf {\mu }\text{m}$ </tex-math></inline-formula> GaN technology. It consists of two-stage amplifier transistors with reconfigurable input, inter-stage and output matching networks. By utilizing the reconfigurable matching networks, the proposed PA circuit divides the frequency band of 2–10 GHz into three continuous sub-frequency bands, and achieves high power added efficiency and gain in each sub-frequency band. As a result, the proposed PA can simultaneously maintain high efficiency and high gain and cover multioctave bandwidth. Moreover, in order to further improve the efficiency, harmonic suppression is used in low-band with open circuit impedance at third harmonic. With these techniques, the proposed PA covers frequency band of 2–10 GHz, delivers an average PAE of 38% at 2–5 GHz, 31% at 5–7 GHz, and 31.5% at 7–10 GHz. Good agreement between simulation and measurement is obtained.

Design of X/Ku Dual-Wideband GaN Power Amplifier MMIC Based on Coupled Multiresonator Matching Networks

This brief presents an X/Ku concurrent dual-wideband power amplifier (PA) monolithic microwave integrated circuit (MMIC) fabricated with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.25{\mu }\text{m}$ </tex-math></inline-formula> GaN-on-SiC technology. The input matching network (IMN) and output matching network (OMN) of the proposed PA are designed based on electric and magnetic coupled symmetric multi-resonator matching networks (MRMNs) respectively to obtain four reflection zeros. Through symmetrical network analysis method, the four reflection zeros of the matching network are equally divided into two sub frequency bands and an optimal dual-wideband matching performance is realized. The proposed PA obtains average saturated output power of 36.9dBm and 35.9dBm in 9GHz–10GHz and 13.5GHz–16GHz. The measured average power-added efficiency (PAE) are 34.8% and 32.6% in 9GHz–10GHz and 13.5GHz–16GHz.

A 2-V 1.4-dB NF GaAs MMIC LNA for K-Band Applications.

A 1.4-dB Noise Figure (NF) four-stage K-band Monolithic Microwave Integrated Circuit (MMIC) Low-Noise Amplifier (LNA) in UMS 100 nm GaAs pHEMT technology is presented. The proposed circuit is designed to cover the 5G New Release n258 frequency band (24.25-27.58 GHz). Momentum EM post-layout simulations reveal the circuit achieves a minimum NF of 1.3 dB, a maximum gain of 34 dB, |S11| better than -10 dB from 23 GHz to 29 GHz, a P1dB of -18 dBm and an OIP3 of 24.5 dBm. The LNA draws a total current of 59.1 mA from a 2 V DC supply and results in a chip size of 3300 × 1800 µm2 including pads. We present a design methodology focused on the selection of the active device size and DC bias conditions to obtain the lowest NF when source degeneration is applied. The design procedure ensures a minimum NF design by selecting a device which facilitates a simple input matching network implementation and obtains a reasonable input return loss thanks to the application of source degeneration. With this approach the input matching network is implemented with a shunt stub and a transmission line, therefore minimizing the contribution to the NF achieved by the first stage. Comparisons with similar works demonstrate the developed circuit is very competitive with most of the state-of-the-art solutions.

An N-Path Sub-GHz Ultra-Low Power Receiver Exploiting an N-Path Notch Filter Topology in 90 nm CMOS

This paper describes an N-path sub-GHz ultra-low power receiver exploiting an N-path notch filter topology in 90nm CMOS process. The receiver achieves the flexibility in the operating frequency due to an adjustable internal impedance matching network with an N-path notch filter. The receiver consists of two current-reused topologies, which greatly simplifies the structure and achieves ultra-low power consumption. Specifically, the receiver incorporates: 1) an amplifier with an N-path notch filter, which acts as the first stage of the receiver to provide an input impedance of 50 Ω without an inductor. This input matching network is frequency flexible and adjustable to suit different frequencies of the input signal. Meanwhile, the N-path notch filter can suppress out-of-band interference to cope with limited frequency bands. 2) N-path passive mixers are reused for simultaneous filtering and down-conversion. 3) Amplifiers are frequency-division multiplexed to amplify both RF and baseband signals simultaneously. Finally, the receiver is fabricated in 90 nm CMOS and operates at 0.6 V supply voltage with a power consumption of 780 μW. The receiver achieves a conversion gain of 41.2 ± 3.2 dB, a noise figure of 5.7 ± 0.3 dB and an OB-IIP3 of 14.6 ± 0.5 dBm. The chip area of the implemented receiver is 0.08 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

25–31 GHz GaN-Based LNA MMIC Employing Hybrid-Matching Topology for 5G Base Station Applications

This letter presents a gallium nitride (GaN) high electron mobility transistor (HEMT)-based three-stage low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) that can apply to the fifth-generation (5G) new radio base station applications. The designed GaN-based LNA MMIC utilizes a hybrid-matching topology with double-shunt capacitors at input and output (I/O) matching networks to achieve broad return loss (RL) and bandwidth characteristics across 5G frequency range two bands. The design is fabricated in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.15~\mu \text{m}$ </tex-math></inline-formula> GaN on silicon carbide technology and attains small signal gains greater than 21 dB, noise figures of 2.4–2.9 dB, 1-dB compression points greater than 19.1 dBm, output third-order intercept points greater than 28.5 dBm, and I/O RLs greater than 10 dB at 25–31 GHz band. The implemented design consumes a power of approximately 300 mW.

Compact and efficient wideband rectifier based on π network with wide input power ranges for energy harvesting

This work introduces a wideband, significant RF-DC conversion efficiency and large DC voltage radio frequency (RF) voltagemultiplier/doubler rectifier for energy harvesting (EH) systems utilizing ROG4003C material and Schottky diode. The input matching network is designed using π network and series resonance circuit. Two wideband rectifiers are designed the first one uses lumped inductors in the π network, and the second design employs distributed rectangular inductors. The π network is connected in series with a Schottky diode to compensate its capacitive reactance, diminish its impedance variation when the frequency or input power varies while the series resonance circuit is used to match the minimized variance to the source impedance (50 Ω). An HSMS2852-based rectifier prototype is tested for verification, obtaining a bandwidth of 31.6 % from 720 to 1050 MHz with 68 ± 2 % at an input power of 3 dBm with a peak saturated DC voltage of 3.6 V and an input return loss (S11) less than −10 dB.The proposed rectifiers provide good performance over a wide input power range between −10 dBm and 5 dBm via various load terminals ranging from 2.5Kohms to 10Kohms. The proposed rectifier is suitable for GSM 900, IoT, UHF ISM 900 MHz, WSN, broadband LTE, and multi-standard systems. Finally, the introduced voltage doublers have a compacted area equal to 1.85 cm2.

Harmonic‐tuned high‐efficiency GaN power amplifier with precise AM‐AM and AM‐PM characteristics

AbstractAn optimal balance between high efficiency and high linearity is one of the main performance metrics of modern base stations to handle the deep compression of the power amplifier (PA) module. In principle, the plethora of amplitude‐to‐amplitude (AM‐AM) and amplitude‐to‐phase (AM‐PM) distortions are issues worth exploring. Therefore, this paper presents a linearized harmonic‐tuned PA that operates at 2.4 GHz. The presented PA utilizes a compact input matching network (IMN) and output MN (OMN) with shunt‐connected tunable resonant circuits augmented by the stabilization network, whose presence greatly reduces the transistor parasitics and high‐order effects. Hence, a joint embodiment of each other gives optimal fundamental impedance matching alongside harmonic terminations and precise AM/PM waveform properties. The measurement results have shown that the fabricated PA exhibits peak saturated output power of 40.9 dBm and peak drain efficiency (DE) of 67%. In addition, the AM‐AM and AM‐PM curves under continuous‐wave excitation yield a gain flatness of 0.5 dB over a 37.5 dBm power range and ±3.5° phase distortion, respectively, when the input power level is swept up to the saturation level of 40 dBm. When driven with a 5 MHz 64‐QAM OFDM signal and 6.9 dB power back‐off, the manufactured PA meets the adjacent channel leakage ratio specification of −30 dBc at an average output power of 34.5 dBm.

A 5.9 mW E-/W-Band SiGe-HBT LNA With 48 GHz 3-dB Bandwidth and 4.5-dB Noise Figure

The theory, design, and implementation of a millimeter-wave (mm-wave) two-stage common-emitter (CE) low noise amplifier (LNA) using a 130-nm silicon-germanium (SiGe):C Bipolar CMOS technology is presented. The LNA was optimized for wideband performance from 62 to 110 GHz for both mm-wave radar/sensing and wireless communication applications. A two-stage broadband noise and impedance matching technique is used to obtain a relativity flat gain (13.5 dB) and noise figure (NF) (4.5 dB) across the E-/W-band. Low-voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$(V_{\text {CC}}=0.7\,\,\text {V})$ </tex-math></inline-formula> and low-power (5.9 mW) operation is achieved by forward biasing the base–collector junction, while the wideband capability is further improved by a T-type input matching network utilizing constant quality factor curves. To the best of authors’ knowledge, the presented LNA has the widest 3-dB bandwidth with the lowest power consumption in the literature for silicon-based E-/W-band LNAs.

Estimation of Harvested RF Energy Based on Survey of Ambient RF Power for Optimized Rectifier Design

This paper presents estimation of harvested RF energy by means of measurement survey and rectifier circuit simulation. The survey was done in an indoor environment in Bangkok, Thailand using a low-cost in-house developed measurement system. From the survey, channel power distribution of a signal with 950 MHz center frequency and 20 MHz bandwidth was created. The maximum time averaged channel power is -7.6 dBm whereas the mean value with maximum signal statistic is -11.1 dBm. A single stage rectifier is simulated with 5 different nominal values of RF input power which is used to optimize the rectifier for maximum RF-to-DC power conversion efficiency. The rectifier composes a Schottky diode, a matching network and a simple load consisting of a resistor and a storage capacitor. Parameters of the simplified LC matching network have been varied to match the rectifier’s input impedance to 50 Ω for various nominal values of the RF input power. In addition, the load resistance was varied according to the nominal RF input power for an optimal power conversion efficiency of the rectifier. The rectifier delivers the highest harvested RF energy with a nominal RF input power of -9 dBm which is a value between the maximum and the mean values from the survey. The DC energy converted from ambient RF energy by the rectifier can be estimated. With this information, it can be assessed what type of applications based on available RF energy can be applied for the test area. This rectifier optimization strategy can be applied to any kind of RF signal since it is based on actual measurement results. Moreover, the proposed rectifier can be designed for reconfigurability regarding nominal RF input power at the location of interest by varying the matching network parameters and the load resistance. In practical applications, the reconfigurable rectifier can maintain a high level of power conversion efficiency over a wide range of RF input power. This can be done by optimizing the rectifier’s input matching network and the load resistance for the highest possible power harvested from the environment where the rectifier is located.

Co‐design of a low noise amplifier with compact substrate integrated waveguide bandpass filtering matching network

This article presents a co-design of a low noise amplifier (LNA) and bandpass filter (BPF) input matching network (IMN) based on quarter-mode and one-eight-mode substrate integrated waveguide (SIW) cavities. The transmission zeros (TZs) of the proposed BPF IMN occur in the stopband and demonstrate improved frequency selectivity compared to conventional methods. Our design can reduce the complexity and circuit sizes of receiving BPFs and LNAs in communication systems, and improve the receiving performance of radio frequency (RF) front-end circuitry. Three different LNAs were fabricated and tested. The proposed LNA features a three-stage compact-size SIW BPF IMN at a center frequency (f0) of 8 GHz. The proposed LNA with a compact SIW BPF IMN exhibits better electrical performance than a conventional LNA (CLNA) with a full-mode (FM) SIW BPF. We found that the small signal gains at f0 of the standalone CLNA, FM SIW BPF cascaded with CLNA, and the proposed LNA were 15.69, 14.72, and 15.18 dB, respectively. The measured noise figure (NF) at f0 of CLNA was 0.86 dB, while the NF of the FM SIW BPF cascaded with CLNA was 2.23 dB, and the NF of the proposed LNA at f0 was 1.71 dB. In addition, the circuit size of the proposed LNA is 48% smaller than that of an FM SIW BPF cascaded with CLNA.

Application of harmonic included CPL‐QPHD model of GaN device for broadband PA design

In this work, a harmonic included canonical piecewise linear (CPL) function based quadratic poly-harmonic distortion (QPHD) model is presented. The proposed model employs the framework of the standard QPHD model, making use of the CPL functions for interpolation of the amplitude of the dominant input signal. Compared with the standard QPHD model, the model described in this work is able to predict transistor behavior at different levels of input powers with one single set of model coefficients. The harmonic information has also been added in this model to make it more complete. The model is validated in terms of both DC and RF behavior through simulated data of a 10 W gallium nitride (GaN) high-electron-mobility transistor (HEMT) over a wide range of load conditions and power levels. In addition, the model is implemented in advanced design system (ADS) with frequency-defined device (FDD), and applied for a broadband power amplifier (PA) design. Chebyshev low-pass topology is used for both input and output matching network design. Finally, a broadband PA is implemented with an average power added efficiency of 66.23%, an average power of 41.09 dBm, and an average gain of 13.09 dB across the operating frequency range from 0.6 to 1.7 GHz. The simulation results of the harmonic included CPL-QPHD model are highly matched with the measurement results of the designed PA, demonstrating the feasibility of applying the proposed model for broadband PA design.

A High Conversion Gain Frequency Doubler Using Transformer-Based Second Harmonic Feedback Technique in 28-nm CMOS

This letter presents a frequency doubler with high conversion gain (CG) and output power, which is fabricated in a standard 28-nm CMOS process. The proposed frequency doubler uses a novel transformer-based second harmonic feedback network (SHFN) to improve CG. The SHFN is inserted between the input matching network (IMN) and output matching network (OMN) of the presented frequency doubler, needing no extra area. The measured results show that the peak CG is 1.2 dB at an output frequency of 56 GHz, and the 3-dB gain bandwidth is 16 GHz from 48 to 64 GHz. The frequency doubler exhibits a maximum efficiency of 10.2% and a saturation output power of 5 dBm with dc power consumption of 25 mW and a 0.9-V power supply. The doubler occupies an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.43\times0.38$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , with a core area of 0.047 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Analysis and design of a 55–74 GHz ultra‐compact low‐noise amplifier using highly asymmetric transformers

This letter presents a low-noise amplifier with a 3 dB-bandwidth, from 55 to 74 GHz, excellent noise performance and low power consumption based on a three-stage common-source topology. For the first time to the authors' best knowledge, an analytical equation that also considers the gate–drain capacitance is derived for the employed shunt–series transformer feedback input matching network. To enable shunt–series transformer feedback matching without significant gain reduction a highly asymmetric transformer is designed. Furthermore, a compact transformer-implemented T-shaped output matching network is investigated to minimize the required area. To prove these concepts, the circuit has been fabricated in a 22 nm fully depleted silicon-on-insulator technology. Thanks to the transformer-based matching, an ultra-compact active footprint of 0.039 mm2 is achieved. At a power consumption of 8.4 mW from a 0.41 V supply an average noise figure of 4.8 dB and a peak gain of 14.2 dB has been measured. In- and output matching better than −10 dB over the 19 GHz wide 3 dB-bandwidth are demonstrated.

A K-band broadband low noise amplifier with 18.8dB gain and -13dBm IP&lt;sub&gt;1dB&lt;/sub&gt; in 0.13-µm CMOS

A K-band CMOS broadband low noise amplifier (LNA) based on the magnetically coupled resonator (MCR) matching network technique is presented and implemented in 0.13-µm CMOS technology. Such LNA consists of two common-source (CS) pseudo-differential stages, which use the capacitive neutralization technique to enhance the inversion isolation and Gain. The MCR-based input matching network achieves good balance and loss performance by inventing a compensated capacitor and series resistor loaded at the center point of the transformer’s second coil, which improves the linearity and Noise Figure (NF) of the LNA. The measurement NF is 3.7-5.6dB within the frequency range of 20.9-26.2GHz (BW3dB), and the peak gain is 18.8dB. The measured IP1dB is -13dBm at 24GHz with a power consumption of 18mW under 1.2V supply.

A C-Band Broadband Asymmetric Doherty Power Amplifier Using Phase Compensation and Low Q Technology

In this paper, we present a monolithic microwave-integrated circuit (MMIC) asymmetric Doherty power amplifier (ADPA) using 0.25[Formula: see text][Formula: see text]m gallium-nitride (GaN) process with a compact chip size of 2.9 mm × 1.9 mm in wireless transmitters. Two different power amplifiers are adopted to solve the contradiction between the output power and efficiency of the conventional Doherty power amplifier (CDPA). In addition, phase compensation and low Q impedance inverting network (IIN) technology are used in the input and output matching networks, respectively, to expand the bandwidth of the entire ADPA. The post-layout simulation results show that the designed ADPA has a saturation output power 42.5 dBm with 800 MHz bandwidth from 6.6 to 7.4 GHz. The ADPA demonstrates 36.8–41.8% power-added efficiency (PAE), whereas 44–54% drain efficiency (DE) is achieved at saturation power.

High‐efficiency broadband rectifier with compact size for wireless power transfer

AbstractIn this letter, an efficient broadband microwave rectifier with compact size for wireless power transfer is presented. It is proven that the proposed voltage doubler is easier to be matched than the series diode rectifier to achieve a wide bandwidth. In our analysis, the voltage doubler itself is already matched without the input matching network at the lower frequency band. For higher frequency band matching, a short section of microstrip line is connected to the input port of the voltage doubler. Thus, the proposed rectifier can operate over a broad bandwidth. To verify the design concept, a rectifier is fabricated, and the measurement results demonstrate that the power conversion efficiency is greater than 50% from 0.1 to 4.3 GHz at an 18 dBm input power level, and is higher than 70% within a wide bandwidth of 76.9%. In addition, when the input power is 18 dBm, the peak efficiency is 76.36% at 1.4 GHz. The results show that the proposed rectifier has the merits of compact size, broad bandwidth, and high efficiency.

Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

AbstractHigh‐efficiency and high‐linearity three‐stage transformer‐coupled power amplifier (PA) and power combiner for millimeter‐wave applications using 130 nm CMOS technology are presented in the paper. The suggested PA uses transformer coupled for input, inter‐stage, and output matching networks where the inter‐stage matching inductors are utilized to enhance the RF performance. The proposed power amplifier is composed of three stages: first, driver, and power stages. The first stage operates in a class‐C to improve the efficiency and decrease power dissipated while a class‐AB is used in the driver and power stages to maximize the output power. The proposed PA and power combiner designs are suitable for mm‐wave 5G applications. The coupling transformers, inter‐stage matching inductors, and output combiner are analyzed and designed using Ansoft high‐frequency structure simulator (HFSS) and achieve high‐quality factor and high‐coupling coefficient over the frequency range from 26 to 33 GHz. The proposed three‐stage transformer‐coupled power amplifier covers a frequency band from 26 GHz to 33 GHz with a saturated output power of 13.1 dBm, a peak power added efficiency (PAE) equals 19.1%, and a maximum power gain of 13.25 dB. Whereas the proposed power combiner has a saturated output power of 16.3 dBm, a maximum PAE equals 20.5% and a peak gain of 16.5 dB. The proposed three‐stage transformer‐coupled PA and power combiner consume low power of 65 mW and 128 mW, respectively. Moreover, the adjacent channel power ratios (ACPR) of the proposed PA and power combiner equal −30 dBc and −36 dBc, respectively, for 20 MHz channel bandwidth. Finally, the active areas of the proposed power amplifier and power combiner equal 0.25 mm2 and 0.69 mm2, respectively, while the chip areas are 0.55 mm2 and 1 mm2, respectively.