An N-Path Sub-GHz Ultra-Low Power Receiver Exploiting an N-Path Notch Filter Topology in 90 nm CMOS

Abstract

This paper describes an N-path sub-GHz ultra-low power receiver exploiting an N-path notch filter topology in 90nm CMOS process. The receiver achieves the flexibility in the operating frequency due to an adjustable internal impedance matching network with an N-path notch filter. The receiver consists of two current-reused topologies, which greatly simplifies the structure and achieves ultra-low power consumption. Specifically, the receiver incorporates: 1) an amplifier with an N-path notch filter, which acts as the first stage of the receiver to provide an input impedance of 50 Ω without an inductor. This input matching network is frequency flexible and adjustable to suit different frequencies of the input signal. Meanwhile, the N-path notch filter can suppress out-of-band interference to cope with limited frequency bands. 2) N-path passive mixers are reused for simultaneous filtering and down-conversion. 3) Amplifiers are frequency-division multiplexed to amplify both RF and baseband signals simultaneously. Finally, the receiver is fabricated in 90 nm CMOS and operates at 0.6 V supply voltage with a power consumption of 780 μW. The receiver achieves a conversion gain of 41.2 ± 3.2 dB, a noise figure of 5.7 ± 0.3 dB and an OB-IIP3 of 14.6 ± 0.5 dBm. The chip area of the implemented receiver is 0.08 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .