A High Conversion Gain Frequency Doubler Using Transformer-Based Second Harmonic Feedback Technique in 28-nm CMOS

Abstract

This letter presents a frequency doubler with high conversion gain (CG) and output power, which is fabricated in a standard 28-nm CMOS process. The proposed frequency doubler uses a novel transformer-based second harmonic feedback network (SHFN) to improve CG. The SHFN is inserted between the input matching network (IMN) and output matching network (OMN) of the presented frequency doubler, needing no extra area. The measured results show that the peak CG is 1.2 dB at an output frequency of 56 GHz, and the 3-dB gain bandwidth is 16 GHz from 48 to 64 GHz. The frequency doubler exhibits a maximum efficiency of 10.2% and a saturation output power of 5 dBm with dc power consumption of 25 mW and a 0.9-V power supply. The doubler occupies an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.43\times0.38$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , with a core area of 0.047 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .