Input Matching Network Research Articles

A 60 GHz balun low-noise amplifier in 28-nm CMOS for millimeter-wave communication

In this paper, a 60 GHz complementary metal-oxide-semiconductor (CMOS) balun low-noise amplifier (LNA) was implemented for millimeter-wave communication. To improve the gain and noise performance, slow-wave coplanar waveguides (S-CPW) with high quality factor were designed as input, output, and inter-stage matching networks. At the input port, a balun transformer provides additional passive gain while performing the singled-ended to differential conversion. Implemented in a 28-nm CMOS process, simulated results show that the proposed LNA exhibits a simulated linear gain of 16 dB and a noise figure of 5.6 dB at 60 GHz, with a 3-dB gain bandwidth of 5 GHz (58 GHz–63 GHz). The input return loss is better than −25 dB at the central frequency. The simulated input third-order intercept point (IIP3) is −5 dBm. The circuit draws 35 mA from 1 V supply voltage.

A 4–32 GHz SiGe Multi-Octave Power Amplifier With 20 dBm Peak Power, 18.6 dB Peak Gain and 156% Power Fractional Bandwidth

This letter presents the design and characterization results of a multi-octave power amplifier (MOPA) fabricated in a 0.13- $\mu \text{m}$ SiGe-BiCMOS technology. The single-stage power amplifier is implemented as the stack of a cascode amplifier combining broadband input matching network with resistive feedback, and a common-base amplifier with base capacitive feedback. Measurement results show that the design delivers a peak saturated output power level of 20.2 dBm, with output of 1 dB compression at 19.4 dBm. The measured 3-dB power bandwidth is from 4 to 32 GHz, covering three octaves. The corresponding power fractional bandwidth (PFBW) is 156%. The measured peak power added efficiency is 20.6%, and peak small-signal gain is 18.6 dB. The fabricated integrated circuit occupies an area of 0.71 mm2. To compare state-of-the-art MOPAs, the power amplifier figure of merit defined by the international technology roadmap for semiconductors (ITRS) is modified to include PFBW and area. To the best of authors’ knowledge, the presented design achieves the highest figure of merit among multi-octave PAs in a silicon-based integrated circuit technology reported in the literature.

A Triple-Band CMOS Power Amplifier Using Multi-Band and Switchable Matching Network for Wireless Mobile

A triple-band CMOS power amplifier (PA) is presented. We propose a design methodology using an input matching network to support triple-band operation at 0.9, 1.8, and 2.4 GHz. We also propose an output matching network for the triple-band operation. Given that 1.8 and 2.4 GHz are the harmonic components when the PA is operating at 0.9 GHz, we design the output matching network to be switchable to suppress the harmonic components at the operating frequency. Using this switchable network, we obtain an optimum power matching point for each of the three operating frequencies. To verify the feasibility of the proposed structure, we designed a PA using a 180-nm RFCMOS process. It was measured using a wideband code division multiple access (WCDMA), Long-Term Evolution (LTE) at a 10/20-MHz bandwidth and wireless local area network (WLAN) 802.11n applications. The measured output power was 27.2/26.6 dBm, and the power-added efficiency (PAE) was 22.9%/30.6% under an adjacent channel leakage ratio (ACLR) of -33 dBc at 0.95/1.8 GHz, respectively, with a WCDMA modulation signal. In the case of an LTE modulation signal, the measured output power was 25.1/23.5 dBm, and the PAE was 27.7%/23.6% under an ACLR of −30 dBc for a 10/20-MHz bandwidth, respectively, at 1.8 GHz. The measured output power was 21 dBm, and the PAE was 20% under an error vector magnitude (EVM) of 3.98% at 2.4 GHz for a WLAN modulation signal. Based on the measured results, we successfully verified the feasibility of the proposed PA.

Miniature Switchable Millimeter-Wave BiCMOS Low-Noise Amplifier at 120/140 GHz Using an HBT Switch

A 120–140 GHz frequency-switchable, very compact low-noise amplifier (LNA) fabricated in a 0.13 µm SiGe:C BiCMOS technology is proposed. A single radio-frequency (RF) switch composed of three parallel hetero junction bipolar transistors (HBTs) in a common-collector configuration and a multimodal three-line microstrip structure in the input matching network are used to obtain a LNA chip of miniaturized size. A systematic design procedure is applied to obtain a perfectly balanced gain and noise figure in both frequency states (120 GHz and 140 GHz). The measured gain and noise figure are 14.2/14.2 dB and 8.2/8.2 dB at 120/140 GHz respectively, in very good agreement with circuit/electromagnetic co-simulations. The LNA chip and core areas are 0.197 mm2 and 0.091 mm2, respectively, which supposes an area reduction of 23.4% and 15.2% compared to other LNAs reported in this frequency band. The experimental results validate the design procedure and its analysis.

Investigation of Input–Output Waveform Engineered Continuous Inverse Class F Power Amplifiers

An in-depth analysis of the continuous inverse Class F power amplifier (PA) accounting for nonlinear input and output active device properties is presented. The analyses show possible ways of exploiting input nonlinearity to improve and maintain PA performance in a broadband operation and propose a flexible source second-harmonic design space which reduces the input matching network (MN) design complexities. Such exploitation of input nonlinearity can also alleviate performance degradation due to dynamic knee behavior of a practical field-effect transistor (FET) in continuous inverse Class F PA operation. The analyses are validated with vector load–pull (VLP) measurements and utilized to implement a broadband PA design. High-drain efficiency (DE) over 75% and output power more than 38 dBm are achieved over 0.8–1.4 GHz at constant 3-dB gain compression.

A Watt-level Broadband Power Amplifier in GaAs HBT Process

A fully integrated Watt-level broadband power amplifier for 6.0~7.1 GHz applications in a 2-μm GaAs HBT technology is presented in this paper. The power amplifier is implemented using paralleled sixteen transistors as main amplifier, to obtain high output power. In order to increase the bandwidth of the PA, two L-networks are adopted as the output matching network, and T-type matching network is used as input matching network. The broadband power amplifier has a small-signal gain of 12 dB at 6.6 GHz, and saturation output power of 29.5~31.4 dBm (0.89~1.38 W) at 6.0~7.1 GHz with a maximum power added efficiency of 41.6% at 6.5 GHz. The power amplifier occupies 1.26 ㎟ (including pads).

A 230–260-GHz Wideband and High-Gain Amplifier in 65-nm CMOS Based on Dual-Peak $G_{{\mathrm{max}}}$ -Core

This paper proposes a wideband and high-gain amplifier design technique based on a dual-peak maximum achievable gain ( $G_{\mathrm{ max}}$ ) core. The proposed technique achieves a power gain close to $G_{\mathrm{ max}}$ at two frequencies simultaneously, thereby enabling the implementation of a wideband and high-gain amplifier. The input, output, and interstage matching networks are designed in a gain compensating manner, considering the gain variation of the dual-peak $G_{\mathrm{ max}}$ -core. The four-stage amplifier based on an identical dual-peak $G_{\mathrm{ max}}$ -core at each stage is implemented in a 65-nm CMOS process. The measured results show a 3-dB bandwidth of 30 GHz (227.5–257.2 GHz), a gain of 12.4 ± 1.5 dB, and a peak power added efficiency (PAE) of 1.6% with dc power dissipation of 23.8 mW, which corresponds to the widest 3-dB bandwidth and gain per stage comparable to those of other reported CMOS amplifiers operating at frequencies above 200 GHz.

A 125–143-GHz Frequency-Reconfigurable BiCMOS Compact LNA Using a Single RF-MEMS Switch

In this letter, a 125–143-GHz frequency-reconfigurable BiCMOS compact low-noise amplifier (LNA) is presented for the first time. It consists of two cascode stages and was fabricated using a 0.13- $\mu \text{m}$ SiGe:C BiCMOS process, which integrates RF-MEMS switches. A systematic general design procedure to obtain a balanced gain and noise figure in both frequency states is proposed. The LNA size is minimized by using only one RF-MEMS switch to select the frequency band and a multimodal three-line microstrip structure in the input matching network. The measured gain and noise figure are 18.2/16.1 and 7/7.7 dB at 125/143 GHz. The power consumption is 36.8 mW. The measured results are in good agreement with simulations.

The Theory of Special Noise Invariants

This paper reports a novel systematic theory of the noise invariants of two-port linear noisy networks under lossless reciprocal input and output impedance transformations. The theory clarifies the relationship between the circuit theory of linear noisy networks and the theory of four noise parameters, which are widely applied in the design of low-noise amplifiers (LNAs). In particular, we prove that the fundamental noise invariants under input and output impedance transformations are the eigenvalues of a permuted version of the noise correlation matrix and that there is no feedback operation that preserves them. Known invariants, such as the minimum equivalent noise temperature ${T}_{{N}{min}}$ and ${N}$ , may be expressed in terms of such eigenvalues. In addition, we provide a complete characterization of the four noise parameters of two-port passive dissipative networks in terms of their gain parameters and derive the condition under which the invariant ${4N}{T}_{{0}}{/}{T}_{{N}{min}}$ of passive nonreciprocal networks is lower than two. We also extend the theory of special noise invariants to LNAs with lossy input matching network. Overall, the impact of the findings emerging from the theory is highlighted through theorems, remarks, circuit examples, and studies on widespread design methodologies.

Negative lumped element matching technique for performance enhancement of ultra-wideband LNA

The paper aims at designing of two stage cascaded ultra-wideband (UWB) low noise amplifier (LNA) by using negative image amplifier technique. The objective of this article is to show the performance improvement using negative image amplifier technique and realization of negative valued lumped elements into microstrip line geometry. The innovative technique to realize the negative lumped elements are carried out by using Richard's Transformation and transmission line calculation. The AWR microwave office tool is used to obtain characteristics of UWB LNA design with hybrid microwave integrated circuit (HMIC) technology. The 2-stage cascaded LNA design using negative image amplifier technique achieves average gain of 23dB gain and low noise Figure of less than 2dB with return loss less than −8dB for UWB 3–10GHz. The Proper bias circuit is extracted using DC characteristics of transistor at biasing point 2V, 20mA and discussed in detail with LNA layout. The negative image matching technique is applied for both input and output matching network. This work will be useful for all low power UWB wireless receiver applications.

Synthesis Technique for Low-Loss mm-Wave T/R Combiners for TDD Front-Ends

A time-division duplex (TDD) transmit/receive (T/R) millimeter-wave (mm-wave) front-end comprises a power amplifier (PA), a low-noise amplifier (LNA), an antenna switch, and appropriate passive matching and combining networks. In this paper, a synthesis methodology is proposed that minimizes the overall losses by combining the PA output and the LNA input matching networks together with the T/R switch into one network. The technique improves mm-wave transceiver performance in terms of PA efficiency and LNA noise figure. The proposed T/R combiner can achieve high linearity and can handle large PA output voltage swings. The architecture can be implemented in any process which provides high integration capability. A Ka-band implementation is demonstrated using 45 nm CMOS silicon-on-insulator that includes a high power, four-stack-based PA and an inductively source-degenerated cascode-based LNA. Within the front-end, the PA achieves saturated output power of 23.6 dBm with peak power added efficiency of 28%, while the LNA achieves NF of 3.2 dB. The overall chip area is 0.54 mm2, including pads.

A Digitally Assisted Dual-Input Dual-Band Doherty Power Amplifier With Enhanced Efficiency and Linearity

This brief presents a dual-input dual-band Doherty power amplifier (DPA) that operates at 850 and 2100 MHz. The presented DPA utilizes a compact input matching network and composite right-left handed phase offset line. This DPA delivers a peak output power of around 44.5 dBm with an efficiency enhancement region upto 9–10 dB output power back off at both the operating frequencies. Further, the phase offset angles between main and auxiliary power amplifiers are controlled digitally at both the operating frequencies in order to improve the efficiency and linearity throughout the back-off region. As compared to the conventional phase offset of 90°, the optimum offset angle of 120° at 850 MHz provides an improvement of 13% in drain efficiency and 8.5 dB in C/IMD3. Similarly, an improvement of 4 dB in C/IMD3 is achieved by digitally setting a phase offset of 80° at 2100 MHz.

Linearity-Enhanced Doherty Power Amplifier Using Output Combining Network With Predefined AM–PM Characteristics

In this paper, a new method is proposed to synthesize a linearity-enhanced Doherty power amplifier (DPA) without deteriorating its efficiency. This method determines the combiner network parameters so that a predefined amplitude-to-phase (AM–PM) characteristic is produced while maintaining proper load modulation and consequently good back-off efficiency. The predefined AM–PM characteristic is chosen to be the inverse of the main transistor to enhance the overall DPA linearity. For proof-of-concept validation purposes, a linearity-enhanced DPA circuit prototype is designed to provide linear overall AM–PM characteristics over the frequency band of 4.7–5.3 GHz. Meanwhile, its input matching network is designed to minimize the amplitude-to-amplitude (AM–AM) distortion by properly selecting the source impedances. The measurement results of the DPA prototype under continuous-wave stimuli reveal AM–PM and AM–AM characteristics with maximum phase and gain compression/expansion below ±1° and ±0.25 dB, respectively, when the input power level is swept up to a saturation level of 39 dBm over 4.9–5.3 GHz. Furthermore, when driven with carrier aggregated signals with modulation bandwidths of up to 160 MHz and a peak-to-average power ratio equal to 7.4 dB, the DPA prototype maintains an adjacent channel leakage ratio of better than −40 dBc with a drain efficiency in the excess of 40% and an average output power of 32 dBm, without resorting to any additional linearization schemes. The proposed DPA methodology paves the road for the application of the DPA technique to 5G massive multiple-input and multiple-output transmitters with relaxed linearity requirements as it avoids the extra complexity and power consumption overhead associated with dedicated linearization schemes.

Design and development of 3 kW pulsed solid-state RF power amplifier using two LDMOS in parallel configuration at 1 MHz

A 3 kW and 1 MHz pulsed solid state RF amplifier has been designed and developed to drive TH581 tetrode tube based RF amplifier to realise 100 kW pulsed RF source. The driver amplifier is operated with 1 ms pulse width at 50 Hz repetition rate. The 3 kW RF power is obtained by operating two Gemini pair LDMOS transistors (VDD=50 V) in parallel configuration at device itself and having single ended topology with common lumped element based input and output matching network. The amplifier delivers 3 kW RF power when fed by 25 dBm RF input drive from the signal generator. This scheme eliminates the need of RF combiner and divider which results in low loss, high efficiency, lesser number of components, simple and compact design.

A Compact Switchable Filtering Diplexer Based on Reused L-Shaped Resonator

A switchable filtering diplexer utilizing a reused resonator is proposed to reduce the size and insertion loss. This diplexer consists of two multi-coupled filters which reuse a switchable L-shaped resonator. The co-design of the input matching network and the shared resonator simplifies diplexer’s architecture and reduces the insertion loss further. The fabricated diplexer demonstrates insertion loss of 1.3 dB@ 2.35 GHz and 1.34 dB@ 3.5 GHz, fractional bandwidth of 25%@ 2.35 GHz and 28%@ 3.5 GHz, respectively. The occupied area is as small as ${12 \times 20}$ mm2. Compared with reported state-of-the-arts, the fabricated diplexer achieves a lower insertion loss and a smaller size simultaneously.

Class-J SiGe <inline-formula> <tex-math notation="LaTeX">$X$ </tex-math> </inline-formula>-Band Power Amplifier Using a Ladder Filter-Based AM–PM Distortion Reduction Technique

In this paper, a class-J power amplifier for operation in the X-band realized in SiGe bipolar technology is presented. The proposed design combines the high efficiency of class-J operation with solutions to mitigate AM-PM distortion down to a level compatible with high spectral efficiency modulation schemes like 64-QAM. The design of a transformer-based output matching network and the trade-off between efficiency and pure class-J operation related to a non-ideal second harmonic termination are discussed. The main sources of AM-PM distortion are identified in the base-emitter and collector-based bipolar junction transistor capacitance variation with power level and solutions that make the design less sensitive to these impairments are proposed. Linear MIM capacitors are used at the power amplifier (PA) core output to realize the proper class-J second harmonic termination, while an input matching network based on a Bessel ladder filter is adopted to make the signal phase at the PA core input less sensitive to base-emitter capacitance variation. A class-J PA previously designed for maximum power-added efficiency (PAE) is used as a reference throughout the paper to highlight the trade-off’s entailed by AM-PM distortion reduction. The designed PA features a peak gain of 15 dB at 10 GHz and 8-to-12 GHz −3 dB bandwidth. The saturated power is 22 dBm with a 33% PAE, while the output $p_{1\,\text {dB}}$ is 19 dBm. The AM-PM distortion at $p_{1\,\text {dB}}$ is 5 degrees.

High‐power broadband graphene non‐Foster circuit enabled class‐J GaN HEMT power amplifier

AbstractThis paper presents high‐power broadband graphene non‐Foster circuit (NFC) enabled Class‐J GaN HEMT power amplifier (PA). A graphene resonant‐tunneling diode (RTD) NFC is proposed to provide negative differential resistance characteristics and to create an effective negative capacitance. The NFC is integrated in the input matching network of the Class‐J GaN HEMT PA to cancel out the transistor input parasitic capacitance so as to enhance PA bandwidth, efficiency, output power, and gain. The PA design is based on Cree's packaged GaN HEMT CGHV40030F biased with drain supply voltage of 50 V at quiescent drain‐to‐source current of 44 mA. The PA operates from 3.4 to 4.0 GHz with center frequency of 3.7 GHz. The effective negative capacitance of the NFC from 3.4 to 4.0 GHz stands at −3.3 to −6.0 pF. An effective capacitance of −3.7 pF has been obtained at 3.7 GHz. The PA has small signal gain of 16.1 dB at 3.7 GHz. Large signal simulation input power sweep from 1 to 33 dBm at 3.7 GHz, indicates that the PA has 57.8% drain efficiency, 54.7% power added efficiency (PAE), 44.6 dBm (28.8 W) output power and 11.6 dB transducer power gain at input power of 33 dBm.

Design of Impedance Matching Networks for RF Applications

This technical paper presents a design and study of impedance matching for RF (radio frequency) circuit application of common-source amplifier topology. Input and output matching networks of the amplifier were designed and computed ensuring unconditional stability. Inductors and capacitors are key passive components that are crucial for impedance matching, and are specifically designed such that they would satisfy the gain requirements at a specific frequency of operation. Impedance matching is necessary in RF circuit design to provide maximum possible power transfer between the source or the generator and the load. Complex tradeoffs among technology specifications and design parameters exist and should be carefully handled when designing the impedance matching networks, to optimize the performance of the amplifier.Â

Highly Linear High-Frequency Low-Noise Amplifier Design at ISM Band

A highly linear high-frequency low-noise amplifier is one of the important components in telecommunication receivers. The purpose of making such amplifiers is to amplify received signal from transmitter (antenna) at an acceptable level. A narrow band highly linear low-noise amplifier was studied and designed in this paper. A BFP720 bipolar transistor from Infineon Company associated with ADS software was used. Low-noise amplifier was initially designed and simulated and its results were obtained. Lumped elements of inductor and capacitor were used in the design of input and output matching network of this circuit, and two amplifier circuits were then designed and some techniques and methods proposed to improve its performance.

A 71–76 GHz wideband receiver front-end for phased array applications in 0.13 μm SiGe BiCMOS technology

This paper presents the design of a millimeter-wave wideband receiver front-end in a 0.13 \(\upmu\)m SiGe BiCMOS technology for phased array applications. The receiver front-end is suitable for a phased array time-division duplexing communication system where both the transmitter and the receiver share the same antenna. The monolithic microwave integrated circuit front-end comprises of quarter-wave shunt switches, a low-noise amplifier (LNA), an active phase shifter and a buffer amplifier. The quarter-wave shunt switch is designed using reverse-saturated SiGe HBTs. The transformer-based LNA utilizes a common-emitter amplifier at the first stage and a cascode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The designed switch is incorporated in the input matching network of the LNA. The active phase shifter consists of variable gain amplifiers driven by a polyphase filter-based quadrature generator. The receiver front-end achieves a measured gain of 18.5 dB and a noise figure of 9 dB with a 3 dB bandwidth of 23 GHz from 56 to 79 GHz. The receiver phase can be tuned continuously from 0\(^{\circ }\) to 360\(^{\circ }\). An output referred 1-dB compression point of \(-\) 7.4 dBm is achieved at 70 GHz. The receiver consumes 116 mW of DC power and occupies a core area of \(1800\,\upmu {\text {m}} \times 475\,\upmu {\text {m}}\).