Input Matching Network Research Articles

An active two-stage class-J power amplifier design for smart grid’s 5G wireless networks

<span>The wireless communication networks in the smart grid’s advanced metering infrastructure (AMI) applications need 5G technology to support large data transmission efficiently. As the 5G wireless communication network’s overall bandwidth (BW) and efficiency depend on its power amplifier (PA), in this work, a two-stage class-J power amplifier’s design methodology that operates at 3.5 GHz centre frequency by utilizing the CGH40010F model gallium nitride (GaN) transistor is presented. The proposed design methodology involves proper designing of input, output, and interstage matching networks to achieve class-J operation with improved power gain over desired BW using the advanced design system (ADS) electronic design automation (EDA) tool and estimating its integration feasibility through active element-based design approach using the Mentor Graphics EDA tool. The proposed PA provides 54% drain efficiency (D.E), 53% power added efficiency (PAE) with a small signal gain of 27 dB at 3.5 GHz and 41 dBm power output with 21 dB of improved power gain across a BW of around 400 MHz using 28 V power supply into 50 Ω load. By replacing the two-stage PA's passive elements with active elements, its layout size is estimated to be (15.5×29.2) μm2 . The results of the proposed PA exhibit its integration feasibility and suitability for the smart grid’s 5G wireless networks.</span>

A High Efficiency Broadband Gallium Nitride Power Amplifier with Harmonic Control technology

ABSTRACT In order to meet the requirements of high efficiency and broadband for the wireless communication system, a high efficiency and broadband gallium nitride power amplifier (PA) is designed and verified. Using the step-matching structure, its bandwidth has been improved. Furthermore, its input matching network is constructed by connecting several microband lines serially to reduce the matching Q value. Meanwhile, the harmonic control network is designed as the output matching network, which is built by a quarter-wave (λ/4) line open circuit and short circuit microwave lines in parallel. Thus, its drain efficiency (DE)can be improved. This design is simulated and tested at 2.2–3 GHz with the gallium nitride (GaN) process. After measuring, it attains an output power (Pout) of 39.5–41.5 dBm, Gain of 10.5–12.5 dB, DE of 65.1%–78.3% with power added efficiency (PAE) of 64.8%–76.2%.

A 2–36 GHz CMOS LNA with π-Network-Based wideband interstage matching technique for software-defined radio systems

With the advance in wireless communication, next-generation software-defined radio (SDR) systems require transceivers to operate in both sub-6GHz and millimeter-wave (mmWave) band and support multiple standards. However, bridging sub-6GHz frequencies with millimeter-wave bands exceeding 30 GHz remains a challenge for conventional wideband LNAs. To surmount this, a 2–36 GHz CMOS low-noise amplifier (LNA) designed for SDR systems is introduced in this paper. An innovative wideband input matching network capable of spanning both frequency domains is proposed. The methodology effectively mitigates the impact of vast parasitic capacitances, achieving wideband input matching against Electrostatic Discharge (ESD) and on-chip decoupling capacitor parasitic. In addition, a π-network-based wideband interstage matching technique is adopted to extend bandwidth of gain. A tri-stage prototype of the proposed LNA, designed using a 40-nm CMOS process, is designed to validate our design strategies. The post-simulation outcomes reveal a peak gain of 14 dB with a -3dB bandwidth ranging from 2 to 36 GHz, equating to a fractional bandwidth of 178 %. The Noise Figure (NF) is commendably uniform across the frequency spectrum, stabilizing at 5 dB. Furthermore, the third-order input intercept point (IIP3) is −4.2dBm to -3dBm across the bandwidth. The performance is achieved with a power of 19.4 mW and within a core area of 0.1 mm2.

Analysis, design, and optimization based on genetic algorithms of a highly efficient dual-band rectenna system for radiofrequency energy-harvesting applications

This paper gives an enhanced Rectenna design that operates at dual-band [2.45 and 5.8] GHz in the ISM (Industrial, Scientific, and Medical) band and is printed on an FR4-Epoxy substrate. This Rectenna design includes two proposed sub-designs for the receiving antenna and rectifier circuit based on the microstrip technology. The first sub-design concerns the microstrip patch antenna (MPA) described by its radiating element as a pentagonal, its ground being affected by a defective ground structure technique, and its polarization manner as circular polarization. This MPA design is analyzed, designed, optimized using genetic algorithms (GAs), simulated under CST MWS (i.e., computer simulation technology microwave studio), and confirmed by another software named HFSS (high-frequency structure simulator). The second sub-design concerns the microstrip rectifier circuit (MRC) that contains an input matching network based on a coupled-line impedance transformer strategy to achieve good adaptation between MPA and MRC, voltage doubler converter using an SMS7630 Schottky diode thanks to its high sensitivity, microstrip interdigital capacitor to mitigate the intrinsic losses due to the lumped elements, harmonic rejection filter based on a stepped-impedance low-pass filter to reject the unwanted harmonics generated by the non-linear behavior of SMS7630, and the resistive load that models the consumption of the system to be fed. This MRC is analyzed, designed, optimized using GAs, and simulated under ADS (Advanced Design System). The effectiveness of the proposed MPA is proven in terms of gain equals 3.06 dBi and 4.683 dBi at 2.45 GHz and 5.8 GHz respectively, and efficiency equals 95.13 % and 96.552 % at 2.45 GHz and 5.8 GHz respectively. The proposed MRC is effective in terms of efficiency at a lower input power value of about 97.18 % and 67.93 % at 2.45 GHz and 5.8 GHz respectively.

3.3-4.3 GHz efficient continuous class-F gallium nitride power amplifier based on simplified real frequency technique and harmonic tuning.

In order to implement the fifth generation (5G) communication system for a large number of users, the governments of many countries nominated the low 5G frequency band between 3.3 and 4.3 GHz. This paper proposes a wideband RFPA by designing the input matching network (MN) and output MN of the device using the simplified real frequency technique (SRFT) and the harmonic tuning network. The load-pull and source-pull is applied at multiple points for 100 MHz intervals over the bandwidth to obtain the optimum impedances at the output and input of the 10W Gallium Nitride (GaN) Cree CGH40010F device. To verify the design, the RFPA is simulated, and the performance is measured between 3.3 and 4.3 GHz. According to experimental findings, the measured drain efficiency (DE) throughout the whole bandwidth ranged from 57.5 to 67.5% at the output power of 40 dBm. Moreover, at the 1 dB compression point between 39.2 and 42.2 dBm output power, the drain efficiency (DE) achieves a high value of 81.2% with an output power of 42.2 dBm at a frequency of 3.3 GHz. The RFPA can obtain a maximum gain of 12.4 dB at 3.5 GHz. The linearity of the RFPA with a two-tone signal is measured and the value is less than -22 dBc all over the band.

Multi-switch-controlled multi-mode TRFE with a high-linearity ATRSW for 2.4-GHz ISM applications

This paper presents a multi-switch-controlled multi-mode transceiver front end (TRFE) designed for the 2.4-GHz industrial–scientific–medical (ISM) band, with a particular focus on enhancing the linearity of the transmit/receive switch (TRSW) on the antenna side. Considering the distinct power levels in the RX/TX paths, the TRSW is designed to be asymmetric. This design not only elevates IP-0.1dB by over 50 % compared to the conventional symmetric topology, but also absorbing its function into the input matching network (IMN) of the low noise amplifier (LNA), thereby minimally impacting the noise figure (NF) of the RX chain. For the TX path, the high-pass component of the power amplifier (PA) output matching network (OMN) is repurposed, with a singular inductor being redeployed to serve as an inductive ESD safeguard. Moreover, the driving stage employs a passive gain-boosting technique, which elevates the gain by 3 dB compared to the traditional cascode structure. For verification, this TRFE is fabricated in 0.18-μm CMOS with a die size of 1.53 mm2. It achieves a NF of 2.4 dB and a RX gain of 16.7 dB under a 3.3-V supply. A TX gain of 26.2 dB and a saturation output power of 23.3 dBm with a peak power-added efficiency (PAE) of 38.8 % are also demonstrated.

A 4-bit active-inductor-based digitally programmable low noise amplifier (AI-DPLNA) with a tunable and reconfigurable structure

In this paper, a band selective, active-inductor-based digitally programmable low noise amplifier (DPLNA) with a reconfigurable structure is presented. The reconfigurablility of the DPLNA is provided by a programmable current steering network, size-scalable cascode core, and input matching network, which are merged together, and along with a programmable active inductor (AI) as a replacement to huge passive inductors, a compact reconfigurable AI-DPLNA structure is achieved. The size-scalable source degenerated cascode structure is used as the core of the proposed DPLNA, and as a part of current steering network, its output current is reused for biasing the programmable active inductor (AI), which acts as the tank circuit for a narrow-band operation. The operation frequency of DPLNA is controlled by AI load and input matching circuit. A 2-bit programmable current steering network combined with the size-scalable cascode core set the operation frequency of the AI by adjusting its transconductance. Another 2-bits control the AI’s capacitance and also configure the input matching network. Using a TSMC 0.18μm CMOS technology, the simulated 4-bit AI-DPLNA gives a frequency band in the range from 1.816 GHz to 2.631 GHz, an input return loss (LRT) greater than 16.37 dB, a gain (S21) from 11 to 12.57 dB, and a minimum noise figure from 2.6 to 4.2 dB. It consumes a power of 11.4 mW to 12.3 mW from a 2 V supply, and occupies a silicon area of 0.0135 mm2. In addition to PVT and post layout simulations, a prototype of the DPLNA is implemented and tested using through-hole parts to verify the reconfigurability of the proposed structure.

Design of dual-band power amplifier based on microstrip coupled-line bandstop filter

This article presents a simple and effective method for designing a dual-band power amplifier (PA). A microstrip coupled-line bandstop filter (BSF) is cascaded with a broadband PA, thus a notched band can be obtained in the wide operating band, realizing a dual-band characteristic of the PA. The simplified real frequency technique (SRFT) is employed to derive a broadband input matching networks covering the requisite frequency band. Appropriate fundamental impedance and second harmonic impedance matching are achieved at the ideal region of the Smith chart. For validation, an experimental prototype is fabricated and tested using a commercial GaN transistor Cree’s CGH40010F. The proposed dual-band PA is operated at 1.95–2.4 GHz and 2.65–3.1 GHz, with 61%–71% measured power-added efficiency (PAE) and 40.5–41.5 dBm of measured output power.

Analysis of source second-harmonic-controlled wideband extended series of continuous modes power amplifiers

In this article, an in-depth analysis is presented for the first time by considering the impact of the input nonlinearity caused by gate-source capacitance (Cgs) on the performance and broadband design of extended series of continuous modes (ESCMs) power amplifiers (PAs). The conclusion of the analysis shows that the drain current waveforms of ESCMs will be altered, resulting in the overlapping region with the voltage waveform and theoretical efficiency becoming a function of the nonlinear factor γ under the influence of input nonlinearity. As a result, compared to the traditional ESCMs PAs, the introduction of nonlinear factor γ has given rise to a wider load design space and source second-harmonic manipulation space, which can achieve bandwidth expansion while reducing the design complexity of input and output matching networks. Subsequently, this conclusion was verified by using a commercially available 10W gallium nitride (GaN) device from Cree to design wideband high-efficiency PAs. The measured results show that in the target frequency band from 0.55 to 3.55 GHz, a drain efficiency of 60.5%–71.5 % and a gain of 9–12 dB can be obtained at a saturated output power of 39–42 dBm.

The Design and Analysis of a 25-Watt Broad-Band GaN HEMT-Based Power Amplifier

This paper presents the novel design and analysis of a 25 W broadband Class-AB GaN HEMT-based power amplifier working over 0.9–1.7 GHz. A large signal model of the Wolfspeed-make GaN HEMT CG2H40025 has been used in this design. The comprehensive design process has been carried out with the help of the Advanced Design System software by Keysight. Instead of conjugately matching the load and source impedance obtained from load-pull analysis of a nonlinear model of CG2H40025, the value of load and source impedance has been tuned with the help of a novel design approach of an ideal matching design approach. Thus, to achieve an output power of more than 25 W and a flat large signal gain of 15.425 ± 0.375 dB, a novel design approach has been employed to create input and output matching networks, maintaining a lower Q value results in broad bandwidth and for determining the load and source impedances. The circuit has been fabricated on Roger’s substrate RO4350B having a dielectric constant of 3.66 and a loss tangent of 0.0031. The unique design approach based on electromagnetic simulation of the circuit at each design step yielded experimental results that agreed very well with the simulated results. The fabricated power amplifier achieves a power-added efficiency of over 54.78% and a drain efficiency of over 55.45% throughout the entire frequency range. It also delivers a maximum output power of 32.18 W at 1.3 GHz. This power amplifier is developed for L-band Foliage Penetrating Radar.

Miniaturized design of multi-octave PA using spoof surface plasmon polaritons

Surface Plasmon Polariton (SSPP), which exhibits subwavelength-scaled field confinement, can be realized at microwave frequencies by ultrathin corrugated metallic strips, providing significant potential for circuit and system miniaturization. A number of SSPP units were employed in this study to design input and output matching networks of a multi-octave RF power amplifier (PA) for the purpose of reducing the overall circuit size. The designed SSPP-based PAs were fabricated and demonstrated to have an output power between 39.1 dBm and 41.8 dBm, and a power added efficiency (PAE) ranging between 60.2 % and 69.8 % in the frequency range of 0.8 GHz to 3.1 GHz, with a size of 35.5 mm * 46.7 mm, which achieves a 47 % size reduction compared to the traditional transmission-line based PA. A highly efficient global optimization method, the Bayesian Optimization (BO), was utilized to further enhance performance. SSPP PA's average output power and PAE have been improved by approximately 0.3 dBm and 2.6 %, respectively. Its overall size remains at the same level. With the use of a 20 MHz 5GNR signal, digital pre-distortion (DPD) has been implemented, and the linearity of the PA has been improved.

Design of a wideband, highly efficient FPA using an asymmetrical open-circuit coupled-lines-based filtering matching network

This study introduces a novel approach to designing a broadband, highly efficient filtering power amplifier (FPA) characterized by unique integrated filtering capabilities. Central to the proposed technique is the utilization of an asymmetrical open-circuit coupled-lines bandpass filter (BPF), serving dual functions as both an input matching network and an output matching network. Notably, this filter design not only enhances the bandpass filtering response but also significantly improves second harmonic rejection performance. To validate this methodology, a broadband FPA is implemented, employing the Cree 10 W GaN HEMT. The proposed FPA, operating between 2.0–3.0 GHz, achieves a peak drain efficiency of 45.9 %-73.26 %, corresponding to a peak output power of 38.5–41.95 dBm at saturation. This marks a notable efficiency enhancement compared to recent research findings. It is believed that the FPA solution is custom-tailored to meet the demanding requirements of modern base stations, striking the balance between improved power-efficiency and good filtering performance.

A symmetrical fully-integrated CMOS doherty power amplifier

This paper presents a new method to enhance the efficiency of a symmetrical doherty power amplifier (DPA) by fully utilizing the current driving capability of a class-C biased peaking amplifier. In this method, with utilization of the passive voltage gain concept, the input matching networks are designed in a way that the peaking path experiences a higher voltage gain than the carrier path, at high powers. As a result, the higher drive voltage of the peaking amplifier compensates for its lower gate bias and identical peak output currents for both amplifiers can be achieved. For demonstration purpose, a two-stage symmetrical DPA with a power utilization factor (PUF) of about unity is designed and fabricated in a standard 0.18-μm CMOS technology. The measurement results at 2.6 GHz show a power gain of 21 dB and an 1 dB compression point of 21.3 dBm. The peak power added efficiency (PAE) is 35% and the PAE at 6 dB power back-off (PBO) is better than 23%.

Design and optimization of spoof surface plasmon polaritons based multi-octave power amplifier using PSO algorithm

In this article, we explore how spoof surface plasmon polaritons (SSPP) theory can be applied to the design of active radio frequency (RF) power amplifiers (PAs). This work utilizes SSPP structures for the design of both input and output matching networks for a multi-octave PA. In order to perform proper impedance matching, the properties of SSPP unit structures are presented and analyzed. A description of the performance of the initial PA has been provided and discussed. Additionally, particle swarm optimization (PSO) is used to further enhance the performance of the PA circuit. In comparison with an embedded gradient method in a commercial tool, the PSO method results in a better optimization result. The fabricated PA is tested and the results indicate that in the frequency range of 0.5 GHz to 2.9 GHz, it achieves an output power of 40.4 dBm to 41.2 dBm, a power added efficiency of 60.5–65%, and an output gain exceeding 10 dB. Compared to recent work, the multi-octave PA in this work broadens bandwidth while maintaining high output power and PAE. To further verify the linearity of the SSPP-based PA, digital pre-distortion (DPD) is implemented. As a result of the DPD, the linearity of the SSPP PA was greatly enhanced.

Design of Impedance Matching Network for Low-Power, Ultra-Wideband Applications

This paper addresses the design of ultra-wideband (UWB) impedance matching networks operating in the unlicensed 3.1–10.6 GHz frequency band for low-power applications. It improves the simplified real frequency technique (SRFT) by adding a realizability check and employing an iterative approach with different initial guesses in optimization to achieve realizable solutions under the requirements of UWB, low-power consumption, and a minimum number of circuit components. The comparison of solutions obtained using the SRFT with published solutions based on the Chebyshev filter theory is presented. It is shown that the optimal SRFT solution requires fewer components in the impedance matching network, maximizes the RF power delivery over the UWB spectrum with a reflection coefficient below −10 dB, and allows for circuit optimization to reduce power consumption. Using the improved SRFT, it demonstrates a systematic approach to find the strategies and limitations of designing the input matching networks for low-power UWB applications using GlobalFoundries 90 nm BiCMOS technology.

A low-cost 24 GHz single-stage amplifier using SICL based stepped impedance matching network

This paper presents a single-stage amplifier using substrate-integrated coaxial line (SICL) technology. It is implemented with a low-cost PCB technique at 23.35–24.05 GHz. The size of the proposed amplifier is 4.9λg×1.1λg where λg is the guided wavelength at the center frequency. In this circuit, a SICL-based bias-tee network is designed where the mounting pads are introduced for the integration of the components, such as transistor and capacitor. Next, with the help of de-embedding techniques, the input and output matching networks are designed in the SICL environment at 24 GHz. The proposed amplifier circuit exhibits 9.2 dB of peak gain with less than 1 dB of gain ripple and more than 10 dB of input/output return losses in the operating frequency band of 23.35–24.05 GHz. Moreover, the elementary blocks of the amplifier are presented in the circuit. Based on the appropriate modeling of the amplifier’s elementary blocks, the simulated and measured results are in good agreement.

Design of high‐efficiency broadband power amplifier based on split‐ring resonator input matching network

AbstractIn this letter, a novel design method of split‐ring resonator (SRR) as the input matching network (IMN) of power amplifier (PA) is proposed. Compared with conventional microstrip lines, SRR is capable of providing necessary harmonic short‐circuit while achieving broadband impedance matching. Applying the even–odd‐mode theory, the impedance transformation characteristics of SRR are analyzed and show SRR can perform accurate impedance matching. To verify the proposed method, a PA is designed and implemented, the input impedance of 10‐W GaN transistor is well matched to the source impedance by the SRR IMN in the operation band of 1.0–3.0 GHz. The measurement results show that the maximum drain efficiency of PA can reach 79.5% with 41.8 dBm of average output power in the operation band.

Compact Asymmetrical Quasi-MMIC Doherty Power Amplifier

This paper presents a compact asymmetrical Doherty power amplifier (PA) based on a quasi-MMIC configuration for 5G sub-6 GHz applications. The proposed Doherty PA is composed of commercial GaN HEMTs and several passive components implemented on a silicon (Si) substrate. In order to achieve size and cost advantages, passive components such as a power divider, input matching networks, output matching networks, and a Doherty combiner are realized using Si-integrated passive device (Si-IPD) technology, which costs about 40% of the budget for the entire GaN MMIC process. For the 3.5 GHz pulsed-continuous waveform signal, the fabricated Doherty PA has an efficiency of 52.6% at a saturated output power of 44.2 dBm. Furthermore, an efficiency of 45.6% was achieved with the output power back-off (OBO) of 7.0 dB. The implemented PA occupies only 8.9 mm × 5.6 mm.

Dual‐band filtering power amplifier with extended passband bandwidths and wide stopband rejection

AbstractThis article presents a dual‐band filtering power amplifier (DB‐FPA) with extended passband bandwidths and wide stopband rejection, which is helpful in reducing the number of microwave components in the dual‐band radio frequency front end, resulting in compact circuit size and low loss. In the designed DB‐FPA, a wideband low‐pass filter is applied as the input matching network (IMN) to provide wideband impedance matching and good stopband rejection, while a dual‐band filtering impedance transformation is adopted as the output matching network (OMN) to provide dual‐band impedance matchings and filtering responses simultaneously. Specifically, the IMN is constructed by high‐impedance transmission‐line sections and low‐impedance open‐circuit stubs. The OMN is designed based on the specific external quality factors and coupling coefficients during two bands, resulting in dual‐band impedance transformations and dual‐band filtering responses. Then, based on the above IMN and OMN, the design procedure of the presented DB‐FPA is summarised. To verify the proposed idea, a novel DB‐FPA has been fabricated and measured. During the two frequency bands, the measured maximum power added efficiencies are 55.11% and 47.78% within 33.0 dBm input power, while the measured peak gains are 15.4 and 14.0 dB within 15.0 dBm input power.

RF-SOI Low-Noise Amplifier Using RC Feedback and Series Inductive-Peaking Techniques for 5G New Radio Application.

This paper presents a low-noise amplifier (LNA) with an integrated input and output matching network designed using RF-SOI technology. This LNA was designed with a resistive feedback topology and an inductive peaking technology to provide 600 MHz of bandwidth in the N79 band (4.4 GHz to 5.0 GHz). Generally, the resistive feedback structure used in broadband applications allows the input and output impedance to be made to satisfy the broadband conditions through low-impedance feedback. However, feedback impedance for excessive broadband characteristics can degrade the noise performance as a consequence. To achieve a better noise performance for a bandwidth of 600 MHz, the paper provided an optimized noise performance by selecting the feedback resistor value optimized for the N79 band. Additionally, an inductive peaking technique was applied to the designed low-noise amplifier to achieve a better optimized output matching network. The designed low-noise amplifier simulated a gain of 20.68 dB and 19.94 dB from 4.4 to 5.0 GHz, with noise figures of 1.57 dB and 1.73 dB, respectively. The input and output matching networks were also integrated, and the power consumption was designed to be 9.95 mA at a supply voltage of 1.2 V.