InP MISFET Research Articles

Carrier density saturation in a [formula omitted] heterostructure

We observe a strong saturation of the carrier density in the quantum well of a Ga 0.25 In 0.75 As / InP MISFET at positive gate voltages. Using a self-consistent Schrödinger/Poisson solver, we model the band structure and find that the saturation is caused by the population of charge states between the gate and the quantum well. We discuss the impact of these charge states on the transport properties, and present a fabrication method that avoids parallel conduction in this heterostructure.

Numerical simulation and modeling of short-channel three-dimensional nano MISFET for the application in ULSI circuits

A complete three-dimensional (3D) numerical model of an InP MISFET has been presented for the application in the future ULSI circuits. The exact potential profile in the channel of 100nm N type InP MISFET has been computed by solving 3D Poisson's equation using boundary value problems. The electric field profile and mobility of the carriers have been studied extensively. The transfer characteristics of the MISFET has been studied numerically and presented in this paper. The drain current is calculated by applying electric field and the effective mobility of the carrier at a particular point. A study of other device parameters like transconductance, drain current vs. drain voltage of the device has been carried out and compared with the existing results. The model is purely a physics based one and overcomes the major limitations of the existing 2D/3D analytical models by providing a more accurate result and this model is validated by comparing with the existing results as well as the experimental results.

Optimization and Interface Characterization of a Novel Oxide-Free Insulated Gate Structure for InP Having an Ultrathin Silicon Interface Control Layer

Attempts were made to characterize and optimize the novel oxide-free insulated gate structure for InP, having an ultrathin Si interface control layer (Si ICL). An in situ X-ray photoelectron spectroscopy (XPS) study indicated that P deficiency took place on the InP surface by the irradiation of a high-energy Si beam during the MBE growth of Si ICL. Based on this, a modified gate structure having an In0.53Ga0.47As cap layer on the InP surface for prevention of phosphorus loss was proposed and its interface properties were investigated. A careful design for quantum state control indicated that the Si ICL thickness should be reduced down to 0.5 nm for the InGaAs cap thickness of 3 nm. In situ XPS spectra showed that no pronounced desorption of As or P took place from the surface in the new gate structure. In situ contactless C–V measurement showed a low and wide interface state density distribution with a minimum of 2×1011 cm-2 eV-1. An InP MISFET test device with a gate length of 2 µm exhibited a maximum gm of 123 mS/mm and a high drain current of 389 mA/mm. These results indicated the effectiveness of the novel oxide-free insulated gate structure for application to InP power MISFETs as well as to surface passivation.

Recent Advances in Insulated Gate Technology for GaAs and InP MISFETs

In this paper, the present status of the GaAs and InP MISFETs is presented. A detailed discussion on the models for the interface states and their origin is first presented to show that the disordered layer on the semiconductor surface should be etched prior to MIS device formation. The beneficial effects of (NH4)2Sx treatment and sulphur passivation are then discussed. A summary of the recent results reported on GaAs and InP MISFETs based on the sulfide treatment are presented indicating their superior characteristics.

Surface Stabilization Of Inp Using Cds Thin Films

AbstractA chemical bath deposition process was used to grow thin (25–200 Å) films of cadmium sulfide on (100) InP from an aqueous solution of ammonium hydroxide, cadmium sulfate, and thiourea at 75–85 °C. Reflection high energy electron diffraction (RHEED) and transmission electron microscopy (TEM) show that ˜30 Å films are amorphous, while thicker films exhibit a cubic polycrystalline microstructure, with a preferred orientation in the [110] direction. X-ray photoelectron spectroscopy (XPS) shows the CdS treatment both removes the native oxides of InP and forms a stabilizing layer which protects the substrate from re-oxidation. Quasistatic capacitance-voltage response of MIS capacitors on InP, with a CdS layer between the insulator and substrate, exhibits well defined regions of accumulation, depletion, and inversion, indicating a high-quality interface region. An experimental Cmin/Cox, value of 0.28 was obtained, compared to the theoretical value of 0.07. The density of interface states (Dit) was reduced from 1012 to 1011 eV−1cm−2 after CdS treatment when calculated by the high-low method. InP MISFETs fabricated using CdS interlayers showed greatly enhanced device performance over untreated MISFETs.

Enhancement mode InP MISFET's with sulfide passivation and photo-CVD grown P3N5 gate insulators

High performance enhancement mode InP MISFET's have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P/sub 3/N/sub 5/ film used as gate insulator. The MISFET's thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 10/sup 4/ seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm/sup 2V/spl middot/s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6/spl times/10/sup 14cm/sup 2/ eV has been attained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

UVCVD dielectric films for InP-based optoelectronic devices

A low-temperature UV-activated dielectric deposition method has been applied to the development of indium phosphide based devices for fibre optics communication links. We describe the fabrication and successful passivation of light transmitters and photodetectors by photochemically deposited insulator films. Mesa-type PIN photodiodes with UVCVD silicon nitride junction passivation have low and very stable dark currents. Avalanche photodiodes with a superlattice multiplication region have also been demonstrated using two silicon nitride layers, with a gain-bandwidth product of 50 GHz. Silicon dioxide by UVCVD has been deposited as a gate insulator for InP MISFETs. Such transistors have been used in hybrid photoreceivers with very high sensitivity (−42.8 dBm at 140 Mbit/s) and have been integrated in a laser-FET OEIC operating at 1300 nm wavelength at data rates up to 10 Gbit/s.

A new encapsulation method of InP during post implantation annealing

This paper describes a new encapsulation method of the surface of InP during post implantation annealing with a 1 μm thick InGaAs layer grown by molecular beam epitaxy. Secondary ion mass spectrometry microanalysis shows that the InGaAs/InP interface remains very stable upon rapid thermal annealing. However, capacitance-voltage measurements on MIS Schottky diodes reveal a wide depletion region in the underlying InP due to donor compensation. The proposed process has been successfully integrated in our technology of InP MISFET.

Electroplated solder joints for flip-chip applications : Edward K. Yung and Iwona Turklik. IEEE Trans. Compon. Hybrids mfg Technol.14(3), 549 (1991)

Silicon nitride has been widely used in microelectronic device fabrication processes for encapsulation, surface passivation and isolation. In this paper we report new applications of plasma-enhanced chemical vapor deposition (PECVD) silicon nitride films that can be deposited at a temperature lower than the soft bake temperature of normal photoresists. Lift-off of the silicon nitride film was carried out using standard positive photoresist. GaAs MESFETs and InP MISFETs with self-aligned gates were successfully fabricated using this lift-off process of low temperature PECVD silicon nitride.

Optimization of GaAs-on-silicon MESFET structures : G. Halkias, et al. Solid-St. Electron.34(10), 1157 (1991)

Silicon nitride has been widely used in microelectronic device fabrication processes for encapsulation, surface passivation and isolation. In this paper we report new applications of plasma-enhanced chemical vapor deposition (PECVD) silicon nitride films that can be deposited at a temperature lower than the soft bake temperature of normal photoresists. Lift-off of the silicon nitride film was carried out using standard positive photoresist. GaAs MESFETs and InP MISFETs with self-aligned gates were successfully fabricated using this lift-off process of low temperature PECVD silicon nitride.

Exhaust gas detoxifying systems used in microelectronics : N. Proust, C. Fresnais and F. Bourdon. Revue Technique Thomson-CSF23(3), 619 (September 1991)

Silicon nitride has been widely used in microelectronic device fabrication processes for encapsulation, surface passivation and isolation. In this paper we report new applications of plasma-enhanced chemical vapor deposition (PECVD) silicon nitride films that can be deposited at a temperature lower than the soft bake temperature of normal photoresists. Lift-off of the silicon nitride film was carried out using standard positive photoresist. GaAs MESFETs and InP MISFETs with self-aligned gates were successfully fabricated using this lift-off process of low temperature PECVD silicon nitride.

On the development of chip-net : Parag Diwan and Rakesh Kumar. Microelectron. J.22(7/8), 105 (1991)

Silicon nitride has been widely used in microelectronic device fabrication processes for encapsulation, surface passivation and isolation. In this paper we report new applications of plasma-enhanced chemical vapor deposition (PECVD) silicon nitride films that can be deposited at a temperature lower than the soft bake temperature of normal photoresists. Lift-off of the silicon nitride film was carried out using standard positive photoresist. GaAs MESFETs and InP MISFETs with self-aligned gates were successfully fabricated using this lift-off process of low temperature PECVD silicon nitride.

A novel lift-off process using low-temperature PECVD silicon nitride for the fabrication of self-aligned gate GaAs MESFETs and InP MISFETs

A novel lift-off process for the fabrication of self-aligned gate GaAs MESFETs and InP MISFETs was developed using low-temperature plasma-enhanced chemical vapor deposition (PECVD) silicon nitride films. The gate areas of the GaAs MESFETs and InP MISFETs were defined by silicon nitride lift-off in a substitutional gate process so that the gate electrodes of the field effect transistors were automatically aligned with the source and drain areas. The lift-off of silicon nitride was made possible by characterizing PECVD silicon nitride at low temperatures and performing the silicon nitride deposition at 60°C which was lower than the soft bake temperature of normal photoresist.

Optimization of the InP/SiO2 interface treatment by (NH4)2Sx for the InP MISFET fabrication technology

In this paper, the InP surface sulfidation by (NH4)2S or (NH4)2Sx solutions is investigated in order to reduce the long-term drain-current-drift of MISFET devices and the interface state density at the InP/SiO2 interface. In order to ensure good reproducibility of this treatment, a full chemical characterization of the ammonium sulfide solutions is proposed. After surface sulfidation, an annealing is done in the photo-CVD chamber before depositing the insulator: at 350 °C the initial InPS4 layer is transformed into a stable In2S3 phase without degradation of the P/In ratio. Thanks to this InP surface processing, the 1 MHz and 10 kHz C(V) characteristics of MIS diodes exhibit a deep depletion regime, Nss = 2 × 1010 eV−1 cm−2, and very little frequency dispersion. These results are very encouraging for the MISFET fabrication process.

Progress in InP MISFET Devices

Recent advances in InP MISFET technology are reviewed in this paper. A significant improvement in the interface properties of insulator-semiconductor system has been shown to result through the selection of insulators compatible with InP. Tho processing conditions are also very important for obtaining good dielectric films with low interface state density for successful operation of these devices. Among the dielectrics yielding the best result are P-doped SiO2 and BN films. A new deposition technique of high temperature insulator like BN using a pulsed ruby laser has been discussed. This technique avoids substrate heating during deposition and consequently reduces P-outdiffusioin from InP surface.

Effects of interface traps on the transconductance and drain current of InP MISFET's

The drain current, transconductance, and output resistance of an InP MISFET are shown to depend strongly on the frequency and amplitude of an AC signal applied to the gate. This dependence exists even though the familiar long-term current drift effect is negligible. To explain this phenomenon a new nonequilibrium interface-trap model is proposed. >

New applications of low temperature PECVD silicon nitride films for microelectronic device fabrication

Silicon nitride has been widely used in microelectronic device fabrication processes for encapsulation, surface passivation and isolation. In this paper we report new applications of plasma-enhanced chemical vapor deposition (PECVD) silicon nitride films that can be deposited at a temperature lower than the soft bake temperature of normal photoresists. Lift-off of the silicon nitride film was carried out using standard positive photoresist. GaAs MESFETs and InP MISFETs with self-aligned gates were successfully fabricated using this lift-off process of low temperature PECVD silicon nitride.

Properties of spin-on glass as an insulator for InP metal-insulator-semiconductor structures

The application of Futurrex IC1-200 spin-on glass as an insulator for InP metal-insu-lator-semiconductor (MIS) structures including InP MIS capacitors and InP MIS field-effect transistors (MISFET’s) was investigated. Preliminary measurements of the elec-trical properties of the spin-on glass were performed using Si MIS structures with the spin-on glass insulator layer. It was found that the spin-on glass which is subjected to a final curing treatment utilizing a rapid-thermal annealing at 600° C for 5 sec in a O2 ambient exhibits the best electrical properties. However, it was demonstrated by sec-ondary ion mass spectroscopy that when done on InP, the 600° C rapid-thermal an-nealing resulted in the outdiffusion of indium and phosphorus into the spin-on glass. The change in the spin-on glass electrical characteristics due to this outdiffusion re-sulted in an instability in the InP MISFET operation.

Depletion and enhancement modes in InP MISFETs for power amplification

Un modele pseudo bidimensionnel est propose afin d’etablir les possibilites dumisfetInP en regimes d’enrichissement et d’appauvrissement et une validation des resultats est obtenue a partir de resultats experimentaux On determine les caracteristiques courant de drain enfonction des tensions drain-source et grille-source ce qui permet d’estimer la valeur maximale du courant de drain et de la tension de claquage qui constituent des parametres importants pour des applications de puissance. De plus, on en deduit les principaux parametres de la structure ainsi que les performances hyperfrequences potentielles. Les resultats montrent que lemisfet InP constitue une possibilite tres interessante pour l’ amplification hyperfrequence de puissance.

Dielectric films on semiconductors: Fluorides on indium phosphide

Abstract Recent advances in InP MISFET technology are highlighted in this paper. It is shown that significant improvement in electrical properties of InP Schottky diodes as well as MIS structures can be achieved through chemical treatment of semiconductor surfaces. This is illustrated with reference to HF and sulphide treatment of InP Schottky diodes. MIS structures with prior HF treatment showed a density of interface state as low as 2 × 1010cm−2eV−1 using Ba0.17Sr0.83F2 gate dielectric. The interface properties are explained from the point of view of chemical bonding in the light of Auger and SEM analysis.