Optimization and Interface Characterization of a Novel Oxide-Free Insulated Gate Structure for InP Having an Ultrathin Silicon Interface Control Layer

Abstract

Attempts were made to characterize and optimize the novel oxide-free insulated gate structure for InP, having an ultrathin Si interface control layer (Si ICL). An in situ X-ray photoelectron spectroscopy (XPS) study indicated that P deficiency took place on the InP surface by the irradiation of a high-energy Si beam during the MBE growth of Si ICL. Based on this, a modified gate structure having an In0.53Ga0.47As cap layer on the InP surface for prevention of phosphorus loss was proposed and its interface properties were investigated. A careful design for quantum state control indicated that the Si ICL thickness should be reduced down to 0.5 nm for the InGaAs cap thickness of 3 nm. In situ XPS spectra showed that no pronounced desorption of As or P took place from the surface in the new gate structure. In situ contactless C–V measurement showed a low and wide interface state density distribution with a minimum of 2×1011 cm-2 eV-1. An InP MISFET test device with a gate length of 2 µm exhibited a maximum gm of 123 mS/mm and a high drain current of 389 mA/mm. These results indicated the effectiveness of the novel oxide-free insulated gate structure for application to InP power MISFETs as well as to surface passivation.