InP High Electron Mobility Transistor Research Articles

Composite channel 100 nm InP HEMT with ultrathin barrier for millimetre wave applications

This study introduces a High Electron Mobility Transistor (HEMT) designed for millimeter-wave applications, utilizing a composite channel structure based on InP and InGaAs-InAs-InGaAs. The proposed device incorporates an ultra-thin 2 nm barsrier layer, a distinctive composite channel topology, and a judicious selection of III-V materials. These features collectively contribute to an improved confinement of electrons within the channel, thereby improving the concentration of two-dimensional electron gas (2DEG), and consequently, enhancing the mobility and speed of the device. The proposed device exhibits a unity current gain frequency (f T) of 249 GHz and a maximum oscillation frequency (f MAX) of 523.9 GHz, accompanied by a current gain of 67.7 dB at 0.1 GHz. The off-state leakage current is maintained within the nanoampere range, and the minimum noise figure (NF MIN) is merely 0.76 dB at 10 GHz. A comparative analysis of DC and RF performance, along with an examination of associated parasitic elements, is conducted among various composite channel HEMTs proposed in recent literature. A quantitative justification is provided for the superiority of InGaAs-InAs-InGaAs channel HEMTs, establishing their heightened f T and f MAX. The proposed InGaAs-InAs-InGaAs channel HEMTs exhibit 1.4 times improved f T and f MAX, coupled with only half the NF MIN in comparison to their InGaAs-InP-InGaAs channel counterparts. To further comprehend the device’s behavior under varying RF conditions, a frequency-dependent intrinsic Field-Effect Transistor (FET) model is presented. This model facilitates the analysis of the device’s performance and allows the identification of the impact of individual parameters on the overall system.

Origin and suppression of kink effect in InP high electron mobility transistors at cryogenic temperatures

The kink effect is a phenomenon that typically occurs in InP-based InAlAs/InGaAs high electron mobility transistors (HEMTs) at cryogenic temperatures. It results in higher output conductance (gDS) and non-monotonic behavior. This Letter discusses the origin and suppression of the kink effect in InP HEMTs at cryogenic temperatures, which is linked to the structure of gate recess passivation. At room temperature, two devices with different gate recess passivation structures show similar characteristics. However, a temperature-sensitive kink is observed in the non-passivated gate recess structure, leading to the discontinuous transconductance (gm) and the non-monotonic threshold voltage (Vth) shifts. Based on pulsed and static (non-pulsed) measurement data, surface traps and impact ionization in the high-field region are identified as the origin of the kink effect. Specifically, a positive Vth shift of +160 mV is caused by surface traps when the temperature drops to 150 K. A negative Vth shift of –60 mV is due to the enhanced impact ionization below 150 K. Conversely, the device with a passivated gate recess has a negligible kink effect and effectively improves discontinuous gm and the non-monotonic Vth shifts (+25 mV) when the temperature drops. Therefore, the device with a passivated gate recess is significant for suppressing the kink effect and maintaining the stability of the device in variable temperature environments.

Direct parameter extraction method of EEHEMT nonlinear model for InP HEMT

AbstractA direct parameter extraction method of EEHEMT nonlinear empirical model is proposed in this paper. An improved DC model is also presented by considering the channel length modulation parameter () as a function of gate‐to‐source voltage. Model verification is carried out by comparison of measured and simulated current–voltage characteristics and S‐parameters. Good agreement is obtained between the measured and modeled results for 2 × 15 μm gatewidth (number of gate fingers × gatewidth) 70‐nm gatelength InP high electron mobility transistors (HEMT). An increased accuracy in modeling the I–V and RF characteristics is also obtained in the proposed model, compared with the conventional one.

Optimization of Channel Structures in InP HEMT Technology for Cryogenic Low-Noise and Low-Power Operation

We report the impact from channel composition on the cryogenic low-noise performance at low dc power for a 100-nm gate-length InGaAs-InAlAs-InP high-electron mobility transistor (HEMT). Two indium (In) channel compositions, 65% and 80%, were studied by dc and RF characterization at 300 and 5 K. For the cryogenic low-noise optimization, it was important to increase the transconductance to gate–source capacitance ratio in the weak inversion region implying that a higher maximum cutoff frequency in the HEMT does not guarantee lower noise. The HEMT noise performance was obtained from noise measurements in a hybrid three-stage 4–8-GHz ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> -band) low-noise amplifier (LNA) down to 300- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W dc power dissipation. While the HEMT LNA noise performance for both the channel compositions at 300 K was found to be comparable, the HEMT LNA at 5 K with 65% In channel showed a minimum noise temperature of 1.4 K, whereas the noise temperature in the HEMT LNA with 80% In channel HEMTs increased to 2.4 K. The difference in the noise became more pronounced at reduced dc power dissipation. The ultralow dc power of 300 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W demonstrated for a cryogenic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> -band LNA with an average noise temperature of 2.9 K and 24-dB gain is of interest for future qubit read-out electronics at 4 K.

Performance Improvement by SiO₂ Hardmask in 100-nm InP-Based HEMTs for TMIC Applications

Benzocyclobutene (BCB) has been widely used as passivation and interlayer dielectric for sub-millimeter-wave applications and terahertz monolithic microwave integrated circuits (TMICs). In this work, the influence of BCB passivation on 100-nm InP-based high-electron-mobility transistors (HEMTs) was investigated. A set of 100-nm HEMTs with different gate recess structures were fabricated and compared. A SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> hard mask was adopted in the gate recess, which contributed to an improved device performance after BCB passivation. DC and RF performances were characterized before and after BCB passivation. The results show that BCB passivation in the recess region degraded InP HEMTs’ performance, and a better performance was achieved by the SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> hard mask. For traditional devices, of which the gate recess was exposed to silicon nitride (SiN <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\textit{x}}\text{)}$</tex-math> </inline-formula> and BCB passivation layers, both dc and RF performances were deteriorated drastically even though the thickness of SiN <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\textit{x}}$</tex-math> </inline-formula> passivation layer was increased from 20 to 50 nm. However, the SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> hard mask preserved the device performances to a great degree, with only degradation by increased parasitic capacitances according to the small-signal equivalent model. In addition, the threshold voltage shift after BCB passivation was suppressed by the SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> hard mask. Thus, a device structure suitable for BCB passivated TMIC applications is proposed and validated.

Influence of Spacer Thickness on the Noise Performance in InP HEMTs for Cryogenic LNAs

InP high electron mobility transistors (InP HEMTs) with different spacer thickness 1 to 7 nm in the InAlAs-InGaAs heterostructure have been fabricated and characterized at 5 K with respect to electrical dc and rf properties. The InP HEMT noise performance was extracted from gain and noise measurements of a hybrid low-noise amplifier (LNA) at 5 K equipped with discrete transistors. When biased for optimal noise operation, the LNA using 5 nm spacer thickness InP HEMTs achieved the lowest average noise temperature of 1.4 K at 4–8 GHz. The InP HEMT channel noise was estimated from the drain noise temperature which confirmed the minimum in noise temperature for the 5 nm spacer thickness InP HEMT. It is suggested that the spacer thickness acts to control the degree of real-space transfer of electrons from the channel to the barrier responsible for the observed noise variation in the cryogenic InP HEMTs.

Heterogeneous integration of InP HEMTs on quartz wafer using BCB bonding technology

Heterogeneous integrated InP high electron mobility transistors (HEMTs) on quartz wafers are fabricated successfully by using a reverse-grown InP epitaxial structure and benzocyclobutene (BCB) bonding technology. The channel of the new device is In0.7Ga0.3As, and the gate length is 100 nm. A maximum extrinsic transconductance g m,max of 855.5 mS/mm and a maximum drain current of 536.5 mA/mm are obtained. The current gain cutoff frequency is as high as 262 GHz and the maximum oscillation frequency reaches 288 GHz. In addition, a small signal equivalent circuit model of heterogeneous integration of InP HEMTs on quartz wafer is built to characterize device performance.

Effect of Fixed Charges at Interface Between InP and Bonding Layer on Heterogeneous Integration of InP HEMTs

DC performances of depletion-mode 100 nm In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As/InP high electron mobility transistor (HEMT) heterogeneously integrated to silicon substrate by SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bonding were investigated by using numerical simulation. Effects of fixed charges at the InP/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface, the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bonding interface, and the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface on HEMT are compared. Among these charges, dc characteristics of HEMT are most sensitive to fixed charges at the InP/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface. With the density of negative fixed charges at the InP/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface increasing from - 5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> to - 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , the energy band exhibits an upward bending and leads to a decrease of electron concentration in the channel. The threshold voltage shifts from -1.03 to -0.85 V and the output current exhibits a decrease of 96 mA/mm under the gate bias of 0 V; meanwhile, the breakdown voltage increases from 4.4 to 6.5 V under the gate bias of -1.6 V. A shift of C- V curves in pace with transfer characteristic curves further confirms that the two-dimensional electron gas (2DEG) channel of HEMT is indeed influenced by fixed charges at the InP/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface. As a comparison, the other two charges exhibit a relatively weak influence, where the increase of charges at the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bonding interface results in a 36 mV shift of threshold voltage and 20 mA/mm decrease of output current, and the charges at the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface only cause 6 mV shift of threshold that can almost be ignored. We proposed an appropriate increase of InP layer thickness to mitigate the impact of fixed charges on the transfer and output characteristic of HEMTs.

InP HEMTs for Sub-mW Cryogenic Low-Noise Amplifiers

This paper reports on a 100-nm gate length InP high-electron-mobility transistor (HEMT) technology for cryogenic low-noise amplifiers (LNAs) with ultra-low power dissipation of $112~\mu \text{W}$ . This result was obtained by using 100-nm gate length InP HEMTs with improved transconductance at low drain current through a scaled-down gate-channel distance while maintaining a low gate leakage current with the use of an InP etch stop layer and Pt gate metal. The noise performance of InP HEMTs was demonstrated in a 4–8 GHz (C–band) three-stage hybrid LNA at the ambient temperature of 5 K. At a dc power dissipation of $300~\mu \text{W}$ , the average noise temperature was 2.8 K with 27 dB gain. At a dc power dissipation of $112~\mu \text{W}$ , the LNA exhibited an average noise temperature of 4.1 K with a gain of 20 dB. The presented results demonstrate the large potential of InP HEMT technology for sub-mW cryogenic LNA design.

Impacts on access resistance of InP high electron mobility transistors from wafer processing

In this work, the authors evaluated the access resistance of InP high electron mobility transistors (HEMTs) and their degradation during wafer processing. The transfer resistance, which was rarely separated from other components of the total access resistance of InP HEMTs in the literature, was found to be the dominant component of the access resistance. It was also found that the transfer resistance degraded during wafer processing. The selection of the ohmic metal stack and its impact on both the metal-cap contact resistance and the transfer resistance was also investigated. The observations in their experiments and relevant discussions in the report are expected to be useful in the identification of improvement opportunities in both material growth and wafer fabrication of InP HEMTs.

Improving InP High Electron Mobility Transistor Performance by an Inserting Blocking Diode for Terahertz Applications

Improving InP High Electron Mobility Transistor Performance by an Inserting Blocking Diode for Terahertz Applications

0.3-14 and 16-28 GHz Wide-Bandwidth Cryogenic MMIC Low-Noise Amplifiers

We present two monolithic microwave integrated circuit (MMIC) cryogenic broadband low-noise amplifiers (LNAs) based on the 100 nm gate length InP high-electron mobility transistor technology for the frequency range of 0.3-14 and 16-28 GHz. The 0.3-14 GHz three-stage LNA exhibited a gain of 41.6 ± 1.4 dB and an average noise temperature of 3.5 K with a minimum noise temperature of 2.2 K at 6 GHz when cooled down to 4 K. The 16-28 GHz three-stage LNA showed a gain of 32.3 ± 1.8 dB and an average noise temperature of 6.3 K with a minimum noise temperature of 4.8 K at 20.8 GHz at the ambient temperature of 4 K. This is the first demonstration of cryogenic MMIC LNA covering the whole K-band. To the best of the authors' knowledge, the cryogenic MMIC LNAs demonstrated the state-of-the-art noise performance in the 0.3-14 and 16-28 GHz frequency range.

Investigation of breakdown performance in $$L_{g}$$ L g = 20 nm novel asymmetric InP HEMTs for future high-speed high-power applications

In this paper, we investigated the breakdown performance of novel nanoscale asymmetric InP high-electron-mobility transistors (HEMTs). The novel asymmetric InP HEMT features $$\Gamma $$ -gate, heavily doped multilayer cap, $$n^{+}$$ -type In $$_{0.52}$$ Ga $$_{0.48}$$ As source/drain (S/D) regions, InAs-rich composite channel, SiN passivation and double $$\delta $$ -doping planes. The impact of asymmetric gate recess width on DC, RF and breakdown performance of novel asymmetric InP HEMT has been investigated using hydrodynamic carrier transport model along with other physical models such as Shockley–Read–Hall model, recombination models, high-field mobility model and density gradient model. Sentaurus TCAD simulations were carried out at room temperature for gate lengths of 50 and 20 nm in order to analyse the scalability of the new device architecture. In order to consider the quantum effects at nanoscale regime, density gradient model of eQuantum potential was used for TCAD simulations. $$L_{g}$$ = 20 nm proposed HEMT achieved a peak $$g_{m}$$ and $$I_\mathrm{DS}$$ of 3470 mS/mm and 1300 mA/mm, respectively. The proposed HEMT has a $$f_{T}$$ and $$f_\mathrm{max}$$ of 749 and 1460 GHz, respectively. The $$L_{g}$$ = 20 nm proposed HEMT also showed an ON-state and OFF-state breakdown voltages of 2.2 and 4.5 V, respectively, at a gate recess width of 150 nm. To the best of authors’ knowledge, this is the record combination of DC, RF and breakdown performance reported for InP HEMTs which makes them the most suitable transistors for future high-speed high-power applications.

Heterogeneously Integrated W-Band Downconverter

We report a heterogeneously integrated W-band downconverter, consisting of a low noise amplifier (LNA) and a star mixer. An LNA is realized in a 0.1- $\mu \text{m}$ InP high-electron-mobility transistor (HEMT) technology and features the noise figure of ~2.5 dB and gain ≥25 dB at W-band. Star mixer is realized in four-layer interconnect InP heterojunction bipolar transistor (HBT) and diode process. A novel design eliminates electrically large diode ring by utilizing a multimetal configuration. Mixer chiplet is integrated into the LNA carrier wafer using heterogeneous integration, which offers electrically short connection between two technologies. Heterogeneously integrated interconnect or transition has measured a loss of ~0.8 dB up to 96 GHz. Integrated W-band downconverter has measured the conversion gain ≥0 dB from 87 to 100 GHz. This is a first reported integration of InP HBT chiplets into the InP HEMT wafer using heterogeneous integration, as well as first reported a W-band heterogeneously integrated downconverter.

Neutral beam process in AlGaN/GaN HEMTs: Impact on current collapse

In this paper, we report a promising approach for the gate recess process with a suppressed current collapse in GaN-based high electron mobility transistors (HEMTs) by means of neutral beam (NB). A recessed gate structure has been widely studied as a way to realize normally-off operation in GaN, InP, and GaAs-based HEMTs. Since GaN-based materials are usually etched by dry process, plasma-induced damage is a serious concern. NB is free from electrical charges and UV photons, resulting in an accurate control of etching depth and less plasma-induced damages. In this work, we introduce NB irradiation to the gate interface and measured DC and gate-pulsed output characteristics. The results suggest that NB is applicable for the gate recess etching with suppressing the current collapse.

22 nm InAs channel-based HEMTs on InP/GaAs substrates for future THz applications

In this work, the performance of nm InAs channel-based high electron mobility transistor (HEMT) on InP substrate is compared with metamorphic high electron mobility transistor (MHEMT) on GaAs substrate. The devices features heavily doped InAs source/drain (S/D) regions, Si double δ-doping planar sheets on either side of the InAs channel layer to enhance the transconductance, and buried Pt metal gate technology for reducing short channel effects. The TCAD simulation results show that the InP HEMT performance is superior to GaAs MHEMT in terms of , and transconductance (). The 22 nm InP HEMT shows an of 733 GHz and an of 1340 GHz where as in GaAs MHEMT it is 644 GHz and 924 GHz, respectively. InGaAs channel-based HEMTs on InP/GaAs substrates are suitable for future sub-millimeter and millimeter wave applications.

20 nm high performance enhancement mode InP HEMT with heavily doped S/D regions for future THz applications

The DC and RF performance of Lg = 20 nm enhancement mode (E-Mode) In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel high electron mobility transistor (HEMT) on InP substrate with heavily doped In0.52Ga0.48As source/drain regions (S/D) is compared with the performance of conventional HEMT structure. The other features of the device include the use of T-gate, thin layer of platinum sink into the barrier layer, double δ-doping technology and multilayer cap. The Sentaurus TCAD simulations performed at room temperature using physics based drift-diffusion carrier transport model shows that Lg = 20 nm, W = 2 × 10 μm device with heavily doped In0.52Ga0.48 As S/D regions exhibit a 14% improvement in transconductance (gm) and 15% improvement in drain current compared to conventional HEMT structure. Also the proposed device shows 25% improvement in cut-off frequency (fT) and 17% improvement in maximum oscillation frequency (fmax) compared to conventional HEMT structure and this excellent performance is achieved mainly due to the reduction of parasitics such as S/D resistances and also due to the low gate length.

Helicity sensitive terahertz radiation detection by dual-grating-gate high electron mobility transistors

We report on the observation of a radiation helicity sensitive photocurrent excited by terahertz (THz) radiation in dual-grating-gate (DGG) InAlAs/InGaAs/InAlAs/InP high electron mobility transistors (HEMT). For a circular polarization, the current measured between source and drain contacts changes its sign with the inversion of the radiation helicity. For elliptically polarized radiation, the total current is described by superposition of the Stokes parameters with different weights. Moreover, by variation of gate voltages applied to individual gratings, the photocurrent can be defined either by the Stokes parameter defining the radiation helicity or those for linear polarization. We show that artificial non-centrosymmetric microperiodic structures with a two-dimensional electron system excited by THz radiation exhibit a dc photocurrent caused by the combined action of a spatially periodic in-plane potential and spatially modulated light. The results provide a proof of principle for the application of DGG HEMT for all-electric detection of the radiation's polarization state.

First Demonstration of Amplification at 1 THz Using 25-nm InP High Electron Mobility Transistor Process

We report the first ever terahertz monolithic integrated circuit amplifier based on 25-nm InP high electron mobility transistor (HEMT) process demonstrating amplification at 1 THz (1000 GHz) with 9-dB measured gain at 1 THz. This milestone was achieved with a 25-nm InP HEMT transistor, which exhibits 3.5-dB maximum available gain at 1 and 1.5 THz projected $f_{\mathrm {\mathbf {MAX}}}$ .

Impact of the silicon-nitride passivation film thickness on the characteristics of InAlAs/InGaAs InP-based HEMTs

In this research, the DC and RF characteristics for our own InAlAs/InGaAs InP-based high-electron-mobility transistors (HEMTs) with 0-nm, 50-nm, and 200-nm silicon-nitride (Si3N4) passivation films have been investigated comprehensively and systematically. With increasing Si3N4 passivation film thickness, the device exhibits an apparent improvement in the output conductance and a distinct drift of the pinch-off voltage toward a positive value. Especially, the device passivated by using a 50-nm Si3N4 film demonstrates the highest extrinsic transconductance and channel current. The appeared changes of the DC properties can be interpreted as due to the passivationinduced positively-charged surface state increasing the sheet carrier density with the carrier mobility and parasitic resistance of device being deteriorated by long-time high-stress-intensity ion bombardment. Additionally, the degradations of the current-gain cutoff frequency (f T) and maximum oscillation frequency (f max) can be attributed to the drastically-increased parasitic capacitance and resistance induced by the passivation process. This work will be of great importance in fabricating InP HEMTs with high performances.