InP Buffer Layer Research Articles

Direct correlation of defects and dark currents of InGaAs/InP photodetectors

A direct correlation pathway has been established between the material defects and dark currents of InGaAs photodetectors, which is significant for demonstrating the focal plane array with large scale and small pixels. The same photodetector chip was characterized by using emission microscopy and dark current-voltage measurements. The chips with defect emissions perfectly match with those chips showing large dark currents. The defect emissions were observed for the chips with large dark currents, while did not for the chips with low dark currents. The measurement result of the transmission electron microscope reveals that those material defects correlated with the device dark currents were mainly originated from the interface of the substrate and InP buffer layer. This work clarifies the direct correlation of defect types and device performances, which indicates the direction of improving the photodetector materials.

Investigation of the Effect of Doping on Transition Layers of Anisotype GaInAsP and InP Heterostructures Obtained by the Method of MOCVD

When studying doped anisotypic heterostructures with Ga1 – xInxAsyP1 – y layers grown on InP substrates with an InP buffer layer by metal organic chemical vapor deposition, the presence of transition regions is revealed in the Ga1 – xInxAsyP1 – y layer from the side of the substrate in some of the samples, along which the arsenic content (y) increases from the interface with the InP layer to the surface of the structure by a Δy value of up to 0.15, while the content of elements of the third group (x) remains constant.

Strain mapping at the interface of InP/InxGa1-xAs/InP as measured by the scanning transmission electron microscope-moiré fringe method

Recently, the scanning transmission electron microscope-moiré fringe (SMF) method has attracted much interest because of its precise estimation of the local strain distribution of strained semiconducting devices. In this study, by SMF method, we found that the strain was not uniformly distributed in the InxGa1-xAs layer when it was sandwiched between two InP layers. The most notable point is that the In0.53Ga0.47As layer showed compressive strain at the interface with the InP buffer layer, and showed tensile strain at the interface with InP cap layer even though both InP and In0.53Ga0.47As had the same lattice constant.

Anomalous arsenic diffusion at InGaAs/InP interface

The anomalous arsenic (As) diffusion at the In0.53Ga0.47As/InP interface grown by solid source molecular beam epitaxy has been reported in this work. Heterointerface samples were grown using group-V switches of P2 to As2 or to As4. High-resolution x-ray diffraction (XRD), photoluminescence (PL), 3D atom probe (3DAP) and high-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) data have shown that, an up to hundred-nanometer-thick composition-graded InAsyP1-y layer formed in the InP buffer layer for the sample grown by P2 to As2. This observation demonstrates a rapid replacement of P by As atoms at the heterointerface and a deep As diffusion into the lower InP buffer. In contrary, a sharper heterointerface without the composition-graded layer was obtained in the sample grown using P2 to As4. These findings give insight into the distinct properties of different As species in the InGaAs/InP interface growth.

Stimulated Emission in the 1.3–1.5 μm Spectral Range from AlGaInAs Quantum Wells in Hybrid Light-Emitting III–V Heterostructures on Silicon Substrates

Hybrid laser structures with AlGaInAs quantum wells are grown by metalorganic vapor phase epitaxy on Ge/Si(100) “virtual” substrates using GaAs and InP buffer layers. Stimulated emission is achieved under optical pumping of the prepared samples in the range of 1.3–1.5 μm at liquid-nitrogen temperature. The stimulated-emission threshold is 30–70 kW/cm2.

III-V Superlattices on InP/Si Metamorphic Buffer Layers for λ ≈4.8 μm Quantum Cascade Lasers

Metalorganic chemical vapor deposition (MOCVD) growth of InP‐based quantum cascade laser (QCL) structures on a Si (001) substrate is demonstrated by employing a metamorphic InP buffer layer with InAs/InP quantum dots as dislocation filters. Calibration samples consist of a strain‐compensated 11.98 nm In0.365Al0.635As/14.8 nm In0.64Ga0.36As superlattice (SL) structure as well as 5‐stages of the λ ≈ 4.8 µm QCL active region, which are grown atop the metamorphic buffer and are used to assess the structural properties of the SL through high‐resolution X‐ray diffraction and high‐resolution transmission electron microscopy. Full QCL structures with 40‐stage active region are fabricated into edge‐emitting ridge‐waveguide structures and demonstrate low temperature electroluminescence with a FWHM of 48.6 meV.

Стимулированное излучение в диапазоне 1.3-1.5 мкм из квантовых ям AlGaInAs в гибридных светоизлучающих структурах A-=SUP=-III-=/SUP=-B-=SUP=-V-=/SUP=- на кремниевых подложках

AbstractHybrid laser structures with AlGaInAs quantum wells are grown by metalorganic vapor phase epitaxy on Ge/Si(100) “virtual” substrates using GaAs and InP buffer layers. Stimulated emission is achieved under optical pumping of the prepared samples in the range of 1.3–1.5 μm at liquid-nitrogen temperature. The stimulated-emission threshold is 30–70 kW/cm^2.

The impact of interface and border traps on current–voltage, capacitance–voltage, and split‐CV mobility measurements in InGaAs MOSFETs

In this article, we present coupled experimental/simulated results about the influence of interface and border traps on the electrical characteristics and split‐CV mobility extraction in InGaAs MOSFETs. These results show that border traps limit the maximum drain current under on‐state conditions, induce a hysteresis in the quasi‐static transfer characteristics, as well as affect CV measurements, inducing an increase in the accumulation capacitance even at high frequencies where trap effects are commonly assumed to be negligible. Hysteresis in the transfer characteristics can be used as a sensitive monitor of border traps, as suggested by a sensitivity analysis where either the energetic or the spatial distribution of border traps are varied. Finally, we show that mobility extraction by means of the split‐CV method is affected by appreciable errors related to the spurious contributions of interface and border traps to the total gate charge, ultimately resulting in significant channel mobility underestimation. In very narrow channel devices, channel electron spilling over the InP buffer layer can also contribute to mobility measurement inaccuracy.

Influence of doping in InP buffer on photoluminescence behavior of InPBi

InP1−xBix epilayers with 1.0% bismuth concentration were grown on InP(001) substrates by gas-source molecular beam epitaxy. Silicon and beryllium were doped into the InP buffer layer, and their influences on the photoluminescence (PL) emission of InPBi were investigated. The PL emission of InPBi was found to be intensified by beryllium doping into the InP buffer layer. However, there was no influence of silicon doping. To investigate the reason for the PL intensity enhancement of InPBi, the carrier transport behavior at the interface was also discussed.

Strain-driven synthesis of 〈112〉 direction InAs nanowires in V-grooved trenches on Si using InP/GaAs buffer layers

The catalyst-free metal organic vapor phase epitaxial growth of InAs nanowires on silicon (001) substrates is investigated by using selectively grown InP/GaAs buffer layers in V-grooved trenches. A strain-driven mechanism of self-aligned 〈112〉 direction InAs nanowires growing is proposed and demonstrated by the transmission electron microscopy measurement. The morphology of InAs nanowires is tapered in diameter and exhibits a hexagonal cross-section. The defect-free InAs nanowire shows a pure zinc blende crystal structure and an epitaxial relationship with InP buffer layer.

Integration of InP and InGaAs on 300 mm Si Wafers Using Chemical Mechanical Planarization

Integration of III-V high mobility channel materials in complementary metal oxide semiconductors (CMOS) and III-V photonic materials for integrated light sources on Si substrates requires low defect density III-V buffer layers in order to enable epitaxial growth of high crystal quality active layers. For the fabrication of In0.53Ga0.47As n-channel MOSFET on Si, a lattice matched InP buffer layer is one of the most effective approaches when used in combination with the aspect ratio trapping technique, an integration method known for reducing the density of defects formed during relaxation of strain induced by the lattice mismatch between InP and Si. The InP buffer should be planarized in order to improve thickness uniformity and roughness before subsequent deposition of active layers. In this work we discuss the development of InP planarization on 300 mm Si wafers and investigate slurry composition effects on the final oxide loss and condition of the InP surface. To further explore viability of this approach we deposited an epitaxial In0.53Ga0.47As n-MOS channel layer on top of the planarized InP buffer.

Replacement fin processing for III–V on Si: From FinFets to nanowires

In this paper we review the details and results of the replacement fin process technique used to successfully demonstrate InGaAs based channel devices from FinFets to ultra scaled nanowires on 300mm Si substrates. For FinFet devices a Mg p-type doping solution was developed to counteract the unintentional n-type doping of the InP buffer layer which resulted in high source-drain leakage. However, the performance of these devices is found to be limited by the Mg doping as the mobility is degraded. By switching to a GAA architecture the problem of source-leakage through the InP buffer is effectively eliminated and best devices with LG=60nm have a peak transconductance of 1030μS/μm with a SSSAT of 125mV/dec are achieved. A comparison of gate first to gate last processing highlights the importance of using a low thermal budget process to maintain the integrity of the InGaAs/high-k interface. Nanowires with a diameter of 6nm were demonstrated to show quantization induced immunity to Dit resulting in a SSSAT as low as 66mV/dec for 85nm LG devices.

Metamorphic growth of 1.55 μm InGaAs/InGaAsP multiple quantum wells laser structures on GaAs substrates

We fabricate a GaAs-based InGaAs/InGaAsP multiple quantum wells (MQWs) laser at 1.55 μm. Using two-step growth method and thermal cyclic annealing, a thin low-temperature InP layer and a thick InP buffer layer are grown on GaAs substrates by low-pressure metal organic chemical vapor deposition technology. Then, high-quality MQWs laser structures are grown on the InP buffer layer. Under quasi-continuous wave (QCW) condition, a threshold current of 476 mA and slope efficiency of 0.15 mW/mA are achieved for a broad area device with 50 μm wide strip and 500 μm long cavity at room-temperature. The peak wavelength of emission spectrum is 1549.5 nm at 700 mA. The device is operating for more than 2000 h at room-temperature and 600 mA.

(Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of InGaAs/InP Heterostrucures on Si for Advanced CMOS Devices

This study relates to the heteroepitaxy of InP buffer and InxGa1-xAs channel layers on patterned Si substrates using the defect trapping technique. We focused on the optimization and control of the InP buffer layer in STI trenches to obtain low defect density and high mobility InxGa1-xAs channel layer. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.

High vertical yield InP nanowire growth on Si(111) using a thin buffer layer

We demonstrate the growth of InP nanowires on Si(111) using a thin InP buffer layer. The buffer layer is grown using a two-step procedure. The initial layer formation is ensured by using a very low growth temperature. An extremely high V/III ratio is necessary to prevent In droplet formation at this low temperature. The second layer is grown on the initial layer at a higher temperature and we find that post-growth annealing of the buffer layer does not improve its crystal quality significantly. It is found that the layers inherently have the (111)B polarity. Nanowires grown on this buffer layer have the same morphology and optical properties as nanowires grown on InP (111)B substrates. The vertical yield of the nanowires grown on the buffer layer is over 97% and we also find that crystal defects in the buffer layer do not affect the morphology, vertical yield or optical properties of the nanowires significantly.

Epitaxial III-V-on-silicon waveguide butt-coupled photodetectors

We report silicon waveguide butt-coupled p-i-n InGaAs photodetectors epitaxially grown on silicon-on-insulator substrates by metalorganic chemical vapor deposition. The InGaAs absorption layer that is lattice-matched to InP is selectively grown on patterned SOI substrates, employing metamorphic growth of GaAs and InP buffer layers. We measure a dark current of 2.5 μA and a responsivity of 0.17 A/W at 1550 nm wavelength upon -1 V bias voltage, with a 20 μm × 20 μm InGaAs photodetector area. This device exhibits a 3 dB bandwidth of 9 GHz upon -4 V bias voltage. We demonstrate an open-eye diagram at 10 Gb/s data rate upon -4 V bias voltage.

Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10-7 Ω.cm2. Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This work is a significant step towards the integration of InGaAs based devices on a standard CMOS platform.

Growth and characterization of iron-doped semi-insulating InP buffer layers for Al-free GaInP/GaInAs high electron mobility transistors

We characterize the resistivity of InP buffer layers deposited by metal-organic vapor-phase epitaxy for the fabrication of Al-free GaInP/GaInAs high electron mobility transistors (HEMTs). Achieving highly-resistive InP buffer layers on semi-insulating (SI) InP:Fe substrates has long been recognized to be challenging. This is particularly true in HEMT applications because such devices are especially sensitive to the deleterious effects of buffer leakage currents. Our experiments show that impurities arising from the SI InP substrate as well as from reactor parts produce an overall n-type doping concentration of n=1–10×1016 cm−3 near the buffer/substrate interface, which decays exponentially to a level of 4×1014 cm−3 after approximately 1 μm of InP growth. This nonintentional impurity incorporation leads to a parasitic channel in the buffer and a current leakage path for the HEMT structures, regardless of the growth conditions used. Highly-insulating buffer layers could however be obtained with InP doped by Fe at a concentration of 6×1016 cm−3 in a thin region near the InP:Fe substrate. The sheet resistance consequently increased from RS=3 000 Ω/◻ for the not intentionally doped InP layers to RS=9.4×107 Ω/◻ when Fe-doping is used in the buffer layers, a value suitable for the realization of high-speed HEMTs. As a demonstration vehicle, Al-free pseudomorphic T-gate GaInP/GaInAs HEMTs with a 100 nm footprint were fabricated and achieved a cutoff frequency of fT=fMAX∼250 GHz based on a still nonoptimized channel structure featuring a mobility and sheet carrier concentration of 10 000 cm2/V s and 1012 cm−2, respectively. The present work differentiates itself from previous Fe doping studies of InP by clarifying and quantifying the physical processes leading to parasitic conduction in not intentionally doped InP buffer layers grown on InP:Fe substrates.

Localized growth of InAs quantum dots on nanopatterned InP(001) substrates

We present the method of site-controlled growth of InAs quantum dots on InP(001) by solid-source molecular beam epitaxy. InAs dots are positioned using nanopatterns realized by electron beam lithography and dry etching. We have obtained the localized InAs dots for InAs deposit thickness inferior to the critical thickness for the two-dimensional/three-dimensional growth mode transition measured on a flat InP surface, implying that the dots can be actively positioned at predefined nucleation sites. Photoluminescence results show the emission of localized InAs dots on patterns overgrown with a thin InP buffer layer, at a wavelength around 1.5 μm at room temperature.

Real-time monitoring of InAs QD growth procedure on InP substrate by spectral reflectance

Using an in situ spectral reflectance (SR) method, we monitored the growth procedure of InAs QD layer on InP substrate grown by low-pressure metalorganic chemical vapor deposition. The surface reconstruction of the InP buffer layer at 530 °C under P-rich condition was determined by the subtraction SR and explained to be (2 × 4)-like structures composed of the [ 1 1 ¯ 0 ] P-dimers and [1 1 0] In-dimers. The [1 1 0] and [ 1 1 ¯ 0 ] SR signals at different wavelengths showed different behaviors, which was interpreted to be caused by As/P exchange reaction and the other diverse surface processes. This analysis was confirmed by the comparison between SR signal and multibeam optical stress sensor data.