Integration of InP and InGaAs on 300 mm Si Wafers Using Chemical Mechanical Planarization

Abstract

Integration of III-V high mobility channel materials in complementary metal oxide semiconductors (CMOS) and III-V photonic materials for integrated light sources on Si substrates requires low defect density III-V buffer layers in order to enable epitaxial growth of high crystal quality active layers. For the fabrication of In0.53Ga0.47As n-channel MOSFET on Si, a lattice matched InP buffer layer is one of the most effective approaches when used in combination with the aspect ratio trapping technique, an integration method known for reducing the density of defects formed during relaxation of strain induced by the lattice mismatch between InP and Si. The InP buffer should be planarized in order to improve thickness uniformity and roughness before subsequent deposition of active layers. In this work we discuss the development of InP planarization on 300 mm Si wafers and investigate slurry composition effects on the final oxide loss and condition of the InP surface. To further explore viability of this approach we deposited an epitaxial In0.53Ga0.47As n-MOS channel layer on top of the planarized InP buffer.