Abstract
This study relates to the heteroepitaxy of InP buffer and InxGa1-xAs channel layers on patterned Si substrates using the defect trapping technique. We focused on the optimization and control of the InP buffer layer in STI trenches to obtain low defect density and high mobility InxGa1-xAs channel layer. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.
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