InGaAs FinFETs Research Articles

Inversion-mode InGaAs FinFETs for RF applications

In this study, we present an inversion-mode InGaAs FinFETs with transition frequency (f T) = 263 GHz and maximum oscillation frequency (f max) = 70 GHz. In addition, peak transconductance (g m) = 1976 (μS μm−1) and drain-induced barrier lowering (DIBL) = 88 (mV V−1) were also measured at V ds = 0.5 V; subthreshold swing (SS) = 77 and 83 (mV dec−1) was obtained at V ds = 0.05 and 0.5 V, respectively. Immunity to short-channel effects and superior transfer characteristics are attributed to the gate controllability of the fin structure. This work demonstrates the capability of inversion-mode InGaAs FinFETs in the realm of high-frequency applications.

Attainment of low subthreshold slope in planar inversion-channel InGaAs MOSFET with in situ deposited Al2O3/Y2O3 as a gate dielectric

We have demonstrated a record low 85 mV dec−1 subthreshold slope (SS) at 300 K among the planar inversion-channel InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). Our MOSFETs using in situ deposited Al2O3/Y2O3 as a gate dielectric were fabricated with a self-aligned inversion-channel gate-first process. The temperature-dependent transfer characteristics showed a linear reduction of SS versus temperature, with the attainment of an SS of 22 mV dec−1 at 77 K; the value is comparable to that of the state-of-the-art InGaAs FinFET. The slope factor of SS with temperature (m) is 1.33, which is lower than those reported in the planar InGaAs MOSFETs.

Analysis of Mo Sidewall Ohmic Contacts to InGaAs Fins

We present a novel test structure for the study of sidewall ohmic contacts to III–V fins for FinFETs. We apply it to the characterization of the impact of digital etch (DE), used to trim the fin width, and thermal annealing on the contact resistivity of Mo/ $\text{n}^{+}$ -InGaAs fin sidewall contacts. To obtain sidewall contacts, we leave in place the etch mask that is used to define the fins in a reactive ion etching process and deposit conformal Mo around them. We present a model that describes well the electrical characteristics of the test structure. In our results, we find that the specific acid that is used for DE or the number of DE cycles that are performed have a minor impact on contact resistivity. Thermal annealing is found to significantly improve the sidewall contact resistivity, with the best value of $3.7~ \pm ~0.2~ {\Omega } \cdot {\mu } \text{m}^{{2}}$ obtained after annealing at 400 °C. This is about three times higher than the reported contact resistivity for this contact technology with the contact wrapping around the top and the sidewall surfaces of fins, about $1.3~ {\Omega } \cdot {\mu }\text{m}^{{2}}$ . Also, we find that the width of the non-conductive region under the sidewall surface of Mo contact, which we term “deadzone,” can be significantly mitigated by thermal annealing. Our work highlights the importance of understanding sidewall ohmic contact formation for future high-performance InGaAs FinFETs.

Role of quantum capacitance on the random dopant fluctuation induced threshold voltage variability in junctionless InGaAs FinFETs

This paper reports an investigation of the effects of varying different device parameters on the random-dopant-fluctuation (RDF) induced threshold voltage variability (σVT) in junctionless (JL) InGaAs FinFETs. Such investigation is made by means of a 3D numerical device simulator. Both gate length and fin height scaling are found to increase σVT in InGaAs JL FinFETs, similar to that in Si devices, following “Pelgrom’s law” [1]. On the other hand, although the scaling of either fin width (Wfin) or effective oxide thickness (EOT) of the gate insulator reduces σVT in Si JL devices due to enhanced electrostatic integrity; such scaling is found to deteriorate σVT in InGaAs JL FinFETs. Decrease in the density of state capacitance, also known as quantum capacitance, with Wfin or EOT scaling is found responsible for the deterioration of σVT in InGaAs devices.

Total-Ionizing-Dose Effects and Low-Frequency Noise in 16-nm InGaAs FinFETs With HfO2/Al2O3 Dielectrics

Total-ionizing-dose mechanisms are investigated in 16-nm InGaAs FinFETs with an HfO2/Al2O3 gate-stack. Transistors are irradiated up to 500 krad(SiO2) and annealed at high temperatures. Irradiated devices show negative threshold-voltage Vth shifts, subthreshold stretch-out, and leakage current increases. These result from positive charge trapping in the gate oxide and shallow trench insulators, and increases in the interface and border-trap charge densities. Low-frequency noise measurements at different temperatures indicate a significant increase of noise magnitude in irradiated devices at an activation energy of ~0.4 eV. Density functional theory (DFT) calculations strongly suggest that transistor Vth shifts are due primarily to hole trapping at oxygen vacancies in HfO2, and the increased noise is due primarily to O vacancies in Al2O3. Additional contributions to the noise from defects in the GaAs buffer layer are also likely, primarily at low temperatures.

(Invited) Negative Capacitance III-V FinFETs for Ultra-Low-Power Applications

Owing to its superior carrier transport, InxGa1-xAs materials are considered as the potential n-channels to replace Si for future CMOS technologies beyond the 7-nm technology node. Negative capacitance (NC) FETs with steep SS characteristics are extensively studied to lower the supply voltage (Vdd) for ultra-low-power applications. NC effects can be realized by using ferroelectric (FE) materials in the dielectric gate stack. Among the variety of FE materials, hafnium zirconium oxide (HfZrOx-HZO), which can be employed by atomic layer deposition (ALD) technique, is well-known as the most CMOS-compatible material. There have been various reports that show steep switching behaviors by applying HZO materials on both Si and Ge channels. Recently, NC InGaAs MOSFETs with FE HZO have been presented for steep subthreshold slope (SS) behaviors. However, NC effects have not been presented for nonplanar InGaAs FinFETs yet. In this work, we demonstrate NC In0.53Ga0.47As FinFETs with ferroelectric FE HZO as gate dielectric, exhibiting bi-directional sub-60 mV/dec (SS) at room temperature, for the first time. We show minimum SSrev of 23 and SSfor of 34 mV/dec on InGaAs NC FinFETs with 5 nm HZO thin film. III-V NC FinFETs with HZO FE materials can be very promising for extremely high performance and ultra-low-power CMOS applications.

High-performance InGaAs FinFETs with raised source/drain extensions

In this letter we report on high-performance InGaAs FinFETs with optimized on-off trade-off. The InGaAs FinFETs are fabricated on silicon substrate using a CMOS-compatible replacement-metal-gate process. Excellent off-state performance is achieved by introducing source-drain spacers and doped extension regions. Extensions are fabricated using a digital etching process, a cycling etching technique that allows one to carefully control the position of the junction underneath the spacers. FinFETs with gate length of 13 nm show an on-current of 300 μA μm−1 at VDD = 0.5 V and fixed IOFF = 100 nA μm−1, the highest reported for ultra-scaled Si CMOS-compatible III–V FETs.

Gate Bias and Length Dependences of Total Ionizing Dose Effects in InGaAs FinFETs on Bulk Si

We evaluate the total ionizing dose (TID) responses of InGaAs nMOS FinFETs with different gate lengths irradiated with 10-keV X-rays under different gate biases. The largest degradation after irradiation occurs at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = -1 V. Radiation-induced trapped positive charge dominates the TID response of InGaAs FinFET transistors, consistent with previous results for InGaAs multifin capacitors. Shorter gate-length devices show larger radiation-induced charge trapping than longer gate-length devices, most likely due to the electrostatic effects of trapped charge in the surrounding SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> isolation and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> spacer oxides. The 1/f noise measurements indicate a high trap density and a nonuniform defect-energy distribution, consistent with a strong variation of effective border-trap density with surface potential.

In Situ Thermal Atomic Layer Etching for Sub-5 nm InGaAs Multigate MOSFETs.

Thermal atomic layer etching (ALE) was demonstrated on ternary III-V compound semiconductors. In particular, thermal ALE on InGaAs and InAlAs was achieved with sequential, self-limiting fluorination and ligand-exchange reactions using hydrogen fluoride (HF) as the fluorination reactant and dimethylaluminum chloride (DMAC) as the ligand-exchange reactant. Thermal ALE was investigated on planar surfaces and three-dimensional nanostructures. The measured radial etch rates on In0.53Ga0.47As and In0.52Al0.48As vertical nanowires (VNWs) at 300 °C were 0.24 and 0.62 Å/cycle, respectively. An optimized thermal ALE process did not increase the surface roughness after 200 cycles. The etching process also displayed selectivity and orientation dependence. This new thermal ALE process in combination with in situ atomic layer deposition (ALD) was used to fabricate InGaAs gate-all-around structures with minimum width down to 3 nm. The in situ ALE-ALD process produced a sharp vertical MOS interface. Finally, the merits of thermal ALE were demonstrated in the fabrication of n-channel InGaAs FinFETs with record ON-state and OFF-state transistor performance. On the basis of this transistor demonstration, thermal ALE shows great promise for high-volume device manufacturing.

Excess OFF-State Current in InGaAs FinFETs: Physics of the Parasitic Bipolar Effect

InGaAs FinFETs are challenged by relatively high leakage current in the OFF state. This originates from band-to-band tunneling (BTBT) at the drain end of the channel that is amplified by a parasitic bipolar effect (PBE) as a result of its floating body. In this paper, we present a simple model of the PBE in InGaAs FinFETs, which captures the key gate length and fin width dependences. Our model accounts for surface recombination at the sidewalls of the fin as well as bulk recombination at the heavily doped source. When compared with experimental results, our model suggests that fin sidewall recombination dominates in long gate length transistors and leads to an exponential gate length dependence of the current gain on the parasitic bipolar junction transistor (BJT). The model enables the extraction of the carrier diffusion length which exhibits the predicted fin width dependence. For short gate length transistors, source recombination is shown to dominate and the parasitic bipolar gain scales with the inverse of the gate length.

InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance

In this paper, we demonstrate InGaAs FinFETs 3-D sequentially (3DS) integrated on top of a fully depleted silicon-on-insulator CMOS. Top layer III-V FETs are fabricated using a Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth. We demonstrate that the low thermal budget of the top layer process does not affect the lower level FETs performance. An on-current of 200 μA/μm (at IOFF = 100 nA/μm and VDD = 0.5 V) is achieved, representing the highest reported for 3DS integrated III-V FETs on silicon, showing a 50% improvement in RON compared to previous work. The achieved improved performance can be attributed to the introduction of spacers, doped extensions underneath the gate region as well as improvements in the direct wafer bonding technique.

Pulsed-Laser Induced Single-Event Transients in InGaAs FinFETs on Bulk Silicon Substrates

The pulsed-laser single-event transient response of InGaAs FinFETs on bulk silicon substrates is investigated. Charge collection due to a source–drain shunt effect and drain-to-substrate junction charge collection contribute to the observed transients. The transient response of these silicon substrate devices is compared to that of InGaAs FinFETs on semi-insulating substrates. Faster transients with reduced peak currents and peak widths are observed on the silicon substrate devices. Simulations show hole collection by the silicon substrate. This reduces the amount of source-barrier lowering and bipolar-amplification relative to other III–V devices. Moreover, the reduced hole lifetime in the GaAs buffer layer also contributes to the relative reduction of the bipolar amplification in these devices.

InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities.

III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal–organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n+ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec.

Excess Off-State Current in InGaAs FinFETs

We present a detailed study of the off-state leakage current in scaled self-aligned InGaAs FinFETs. In long-channel devices, band-to-band tunneling at the drain-end of the channel is shown to be the root cause of excessive off-state current. This conclusion emerges from its characteristic electric field and temperature behavior and the absence of gate length and fin width dependencies. In short-channel devices, off-state current is significantly larger and it increases as the gate length shortens or the fin widens. We attribute this behavior to current multiplication through the gain of a floating-base parasitic bipolar transistor that is present inside the MOSFET. We extract the bipolar current gain which in short-channel devices is found to increase as the gate length shortens and decrease as the fin width narrows. In long channel devices, the current gain drops exponentially due to base recombination. This has allowed us to extract the diffusion length of electrons in the body of the transistor.

Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability

Three cross sections (rectangular, bullet shaped, and triangular), resulting from the fabrication process, of nanoscale In0.53Ga0.47As-on-insulator FinFETs with a gate length of 10.4 nm are modeled using in-house 3-D finite-element density-gradient quantum-corrected drift–diffusion and Monte Carlo simulations. We investigate the impact of the shape on ${I}$ – ${V}$ characteristics and on the variability induced by metal grain granularity (MGG), line-edge roughness (LER), and random dopants (RDs) and compared with their combined effect. The more triangular the cross section, the lower the OFF-current, the drain-induced-barrier-lowering, and the subthreshold slope. The ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio is three times higher for the triangular-shaped FinFET than for the rectangular-shape one. Independent of the cross section, the MGG variations are the preeminent fluctuations affecting the FinFETs, with four to two times larger $\sigma {V}_{T}$ than that from the LER and the RDs, respectively. However, the variability induced threshold voltage ( ${V}_{T}$ ) shift is minimal for the MGG (around 2 mV), but ${V}_{T}$ shift increases 4-fold and 15-fold for the LER and the RDs, respectively. The cross-sectional shape has a very small influence in ${V}_{T}$ and OFF-current of the MGG, LER, and RD variabilities, both separated and in combination, with standard deviation differences of only 4% among the different device shapes. Finally, the statistical sum of the three sources of variability can predict simulated combined variability with only a minor overestimation.

Scaling Effects on Single-Event Transients in InGaAs FinFETs

The single-event-transient response of InGaAs FinFETs with different fin widths is examined using pulsed-laser and heavy-ion irradiation. Devices with wider fins collect more charge in both environments. Quantum-well structures confine charge collection in the channel, and determine the sensitive volume. Simulations show that the charge density produced by irradiation is similar for devices with different fin widths, but more charge is collected by wider fin devices due to the larger channel volume. Charge accumulated in the buffer and substrate layers modulates the body potential, altering the degree of back-gate control, leading to additional effects associated with charge accumulation in wider fin devices. Optical simulations for a model system suggest that optical phenomena in the fins should be considered for laser testing. These include optical interference, plasmonic enhancement at the metal–dielectric interfaces, and enhanced electron–hole pair recombination due to multiple reflections in multigate devices with nanoscale dimensions.

A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs

We have developed a scalable gate-last process to fabricate self-aligned InGaAs FinFETs that relies on extensive use of dry etch. The process involves F-based dry etching of refractory metal ohmic contacts that are formed early in the process. The fins are etched in a novel inductive coupled plasma process using BCl3/SiCl4/Ar. High aspect ratio fins with smooth sidewalls are obtained. To further improve the quality of the sidewalls and shrink the fin width, digital etch is used. Through this process flow, we have demonstrated FinFETs with ${L} _{{g= 20}}$ nm and fin width as narrow as 7 nm with high yield. Good electrostatic characteristics are obtained in a wide range of device dimensions. In devices with 7 nm fin width, record channel aspect ratio, and transconductance per unit footprint are obtained.

Understanding Charge Collection Mechanisms in InGaAs FinFETs Using High-Speed Pulsed-Laser Transient Testing With Tunable Wavelength

A tunable wavelength laser system and high-resolution transient capture system are introduced to characterize transients in high-mobility MOSFETs. The experimental configuration enables resolution of fast transient signals and new understanding of charge collection mechanisms. The channel layer is critical in the charge collection process for the InGaAs FinFETs examined here. The transient current mainly comes from the channel current, due to shunt effects and parasitic bipolar effects, instead of the junction collection. The charge amplification factor is found to be as high as 14, which makes this technology relatively sensitive to transient radiation. The peak current is inversely proportional to the device gate length. Simulations show that the parasitic bipolar effect is due to source-to-channel barrier lowering caused by hole accumulation in the source and channel. Charge deposited in the channel causes prompt current, while charge deposited below the channel causes delayed and slow current.

Sub-10 nm plasma nanopatterning of InGaAs with nearly vertical and smooth sidewalls for advanced n-fin field effect transistors on silicon

This work focuses on the nanopatterning of sub-10 nm InGaAs fins by inductively coupled plasma reactive ion etching for advanced III−V n-fin field effect transistors (n-FinFETs) on silicon. First, different chlorine chemistries have been investigated and compared in order to select the most adequate one for the FinFETs process. Following this analysis, the BCl3/SiCl4/Ar mixture was selected for the remaining of the work. Thus, a systematic study of the etching process based on this chemistry has been carried out, and the effects of the experimental conditions on the etching kinetics and the sidewalls quality have been revealed. The optimized results depict 8 nm width fins with smooth (line edge roughness ≈2 nm) and almost vertical (85° ± 1) sidewalls, opening the way for sub-10 nm width InGaAs FinFETs on silicon.

Investigation of Electrical Characteristics on 25-nm InGaAs Channel FinFET Using InAlAs Back Barrier and Al2O3 Gate Dielectric

We investigated an N-type III–V FinFET with a 25-nm In0.53Ga0.47As channel and a 300-nm In0.52Al0.48As barrier layer on an InP substrate. The In0.52Al0.48As barrier layer is used to suppress leakage current from the InP substrate and the 10-nm Al2O3 film deposited by atomic layer deposition (ALD) can be a robust gate dielectric to mitigate interface traps. The on to off current ratio is approximately three orders of magnitude, the subthreshold swing (SS) is 350 mV/dec, and the maximum driving current density is 130 μA/μm at VG = 1.5 V for InGaAs FinFET with a fin width of 40 nm and gate length of 200 nm.