Increased Fault Coverage Research Articles

A Comprehensive Test Pattern Generation Approach Exploiting the SAT Attack for Logic Locking

The need for reducing manufacturing defect escape in today's safety-critical applications requires increased fault coverage. However, generating a test set using commercial automatic test pattern generation (ATPG) tools that lead to zero-defect escape is still an open problem. It is challenging to detect all stuck-at faults to reach 100% fault coverage. In parallel, the hardware security community has been actively involved in developing solutions for logic locking to prevent IP piracy. In logic locking, locks are inserted in different locations of the netlist to modify the original functionality. Unless the correct key is programmed into the IC, the circuit functions incorrectly. Unfortunately, the Boolean satisfiability (SAT) based attack, introduced in [1], can determine the secret key efficiently, and break different logic locking schemes. In this paper, we propose a novel test pattern generation approach using the powerful SAT attack on logic locking. A stuck-at fault is modeled as a locked gate with a secret key, where it can effectively deduce the satisfiable assignment with reduced backtracks under key initialization of the SAT attack. The input pattern that determines the key is a test for the stuck-at fault. We propose two different approaches for test pattern generation. First, a single stuck-at fault is targeted, and a corresponding locked circuit with one key bit is created. This approach generates one test pattern per fault. Second, we consider a group of faults and convert the circuit to its locked version with multiple key bits. The inputs obtained from the SAT attack tool are the test set for detecting this group of faults. Our approach can find test patterns for all hard-to-detect faults that were previously undetected in commercial ATPG tools. The proposed test pattern generation approach can efficiently detect redundant faults as well. We demonstrate the effectiveness of the approach on ITC'99 benchmarks. The results show that we can detect all the hard-to-detect faults and identify redundant faults and a 100% stuck fault coverage is achieved. In addition, we show that test generation time saving becomes significant for Approach 2 as multiple faults help reduce or remove conflicts.

A Statistical Approach of Analog Circuit Fault Detection Utilizing Kolmogorov–Smirnov Test Method

This work presents a testing technique based on ‘Kolmogorov–Smirnov’ (K–S) test for detection of parametric faults in analog circuits. The proposed method is a time-domain signal processing technique that compares the statistical similarity in terms of ‘Empirical Cumulative Distribution Function’ (ECDF) of the outputs of the circuit when the input of the circuit is a random analog signal. ‘Multivariate Adaptive Regression Splines’ (MARS) technique is used to map the tolerances of functional metrics to the components of the circuit under test (CUT). Two benchmark circuits, i.e., second-order Sallen–Key band-pass filter and weakly nonlinear cascade amplifier are tested to validate the proposed fault detection technique. The proposed statistical approach with the use of random analog signal as input excitation results reduction of complexity for designing input test signal and increases fault coverage in the analog circuit testing. The proposed method is testified experimentally for Sallen–Key band-pass filter. The experimental results are in good agreement with the simulated results.

On‐chip generation of primary input sequences for multicycle functional broadside tests

Functional broadside tests are important for avoiding overtesting of delay faults during the application of scan-based tests. Multicycle tests have advantages in defect detection and test compaction. This study addresses the on-chip generation of primary input sequences for the application of multicycle functional broadside tests to a circuit that is embedded in a larger design. In this study, multicycle functional broadside tests are considered under two types of constraints: (i) functional constraints that the design imposes on the primary input patterns of the circuit, and (ii) test application constraints when direct access to the primary inputs of the circuit is not available, and the application of two or more consecutive primary input patterns requires hardware support. The use of multicycle functional broadside tests also results in an increased fault coverage.

Development of a new automatic fault diagnosis system for fine pattern transmission lines

This paper presents a new automatic fault diagnosis and detection system for fine pattern interconnects. It is verified by performance of the proposed system for COFs (chip-on-films) with width of less than 20 μm and pitch of less than 25 μm as fine pattern transmission lines. The proposed system detects and diagnoses variety of faults such as open, short, near open (mouse bite) and near short (soft short) after fabrication cycle of fine pattern transmission lines. This system consists of RF source, variable gain amplifier (VGA), multi-lead probe card, AC generator, Look-Up Table (LUT), signal processing block, and monitoring block. It also utilizes new techniques to differentiate very small voltage changes due to the faults using VGA and programmable gain amplifier (PGA), and to detect barely detectable far-end near open and near short faults. The proposed system showed very low test overhead and significantly high fault coverage as conventional test systems. It is expected that this system is an effective alternative to decrease test overhead and increase fault coverage for the fine pattern transmission lines.

Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications

Test points are inserted into integrated circuits to increase fault coverage especially in logic built-in self-test schemes. Commercial tools have been developed over the past decade to insert test points in circuits under test, but they are often inefficient and incur unacceptably large area overhead. Our analysis shows that many test points have little or no impact on test coverage. Furthermore, depending on where test points are inserted, they can create a significant area overhead unnecessarily. Therefore, we propose a novel timing-aware framework to evaluate test points’ impact on a design, rank them based on their efficiency, and obtain an optimal configuration of the most efficient test points accurately and rapidly. Specifically, the proposed framework considers not only individual test coverage improvement but also area penalty, path timing, and region in which each test point is inserted. Within this framework, we have two metrics, namely, efficient test point insertion (ETPI) and test point removal estimation (TPRE). The ETPI metric is developed to remove the most inefficient test points inserted in the circuit by commercial tools, thereby minimizing area penalty with very limited test coverage loss. The TPRE metric is introduced to estimate area overhead and test coverage for designs with different percentages (number) of test points removed without the actual insertion of test points and without the need for lengthy circuit simulation, thereby quickly selecting the most effective test point removal scheme and saving significant amount of processing time especially for large circuits. Experimental results, collected by applying the metrics to NXP Semiconductors circuits and academic benchmark circuits, indicate that ETPI can reduce area overhead by up to 95% with test coverage loss as low as 0.57%. In addition, results by applying the TPRE metric indicate that the difference between estimation and actual simulation/synthesis results for area overhead is less than 0.20% for most cases, and the difference between them for test coverage is less than 1% for most cases.

Reconstruction of a functional test sequence for increased fault coverage

Simulation-based sequential test generation procedures address the high computational complexity of sequential test generation by replacing the deterministic branch-and-bound process with lower-complexity processes. These processes introduce new primary input patterns into a functional test sequence in order to increase its fault coverage. This study observes that, even without introducing new primary input patterns, it is possible to increase the fault coverage of a functional test sequence by applying the same primary input patterns in different orders. This is referred to as reconstruction of the sequence. It provides a new low-complexity option for increasing the fault coverage, and thus addressing the high computational complexity of sequential test generation. This study describes a reconstruction procedure that is based on repeating short subsequences of primary input patterns from the sequence. Experimental results demonstrate the effectiveness of the reconstruction procedure in increasing the fault coverage as part of a simulation-based sequential test generation procedure.

Two-Run RAM March Testing with Address Decimation

Conventional march memory tests have high fault coverage, especially for simple faults like stack-at fault (SAF), transition fault (TF) or coupling fault (CF). The same-time standard march tests, which are based on only one run, are becoming insufficient for complex faults like pattern-sensitive faults (PSFs). To increase fault coverage, the multi-run transparent march test algorithms have been used. This solution is especially suitable for built-in self-test (BIST) implementation. The transparent BIST approach presents the incomparable advantage of preserving the content of the random access memory (RAM) after testing. We do not need to save the memory content before the test session or to restore it at the end of the session. Therefore, these techniques are widely used in critical applications (medical electronics, railway control, avionics, telecommunications, etc.) for periodic testing in the field. Unfortunately, in many cases, there is very limited time for such test sessions. Taking into account the above limitations, we focus on short, two-run march test procedures based on counter address sequences. The advantage of this paper is that it defines requirements that must be taken into account in the address sequence selection process and presents a deeply analytical investigation of the optimal address decimation parameter. From the experiments we can conclude that the fault coverage of the test sessions generated according to the described method is higher than in the case of pseudorandom address sequences. Moreover, the benefit of this solution seems to be low hardware overhead in implementation of an address generator.

DESIGN AND IMPLIMENTATION OF TEST PATTERN GENERATOR FOR DESIGN UNDER TEST

The patterns generated by LFSR for BIST as lack of correlation between the test vectors. Hence in order to improve the correlation of the test vector the patterns were generated using gray counter and decoder. In this paper we implement low power BIST for 4-bit multiplier. Main aspect of this is to implement low power BIST with increased fault coverage. This use the gray counter, decoder and accumulator as test pattern generator with changing the seed value for every 2 power m cycle, so for this purpose which use counter for monitoring the number of cycles. Hence the respective area optimization and power reduction can be achieved. Simulation outcome on multiplier circuit show a limiting of area and power than reconfigurable Johnson counter and LFSR. We implement the design using verilog HDL and Tool used for implementation is XILINX 13.2 and simulation is performed by using modelsim.

Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array

Static random access memories (SRAM) are a major constituent in high performance microprocessors and systems-on-a-chip. With scaling of technology, manufacturing process variations in SRAMs are of significant concern. SRAM cells that are marginal due to process variations suffer from stability issues where random thermal noise and random telegraph noise (RTN) become determinant in memory state. This introduces uncertainty in testing, where passing a test does not necessarily mean that SRAM is good. A marginal cell may pass testing, but fail during operation. To address this problem, we introduce a new metric for probabilistic fault coverage. We present simulation methods for measuring such coverage and propose N-detect and multilevel wordline (WL) voltage techniques to increase the detection probability of marginal cells. We demonstrate the benefit of these testing approaches on a sample SRAM array, designed in 32 nm predictive technology models. To simulate marginal cells, we oversample the tail of the process variations distribution. Transient noise simulations show that thermal noise can lead to a fault coverage loss of 20% and RTN can lead to a maximum fault coverage loss of up to 75%. N-detect technique achieves close to a 100% fault coverage at ${n}\,\, {=} 100$ for thermal noise and ${n}\,\,{=} 70$ for RTN. Multilevel WL technique requires 20–30 mV boost in WL voltage during read test to achieve near ideal fault coverage at minimal yield loss. A combination of these techniques is shown to be effective in increasing fault coverage with a tradeoff between test time and yield loss.

Fault Handling in PLC-Based Industry 4.0 Automated Production Systems as a Basis for Restart and Self-Configuration and Its Evaluation

Industry 4.0 and Cyber Physical Production Systems (CPPS) are often discussed and partially already sold. One important feature of CPPS is fault tolerance and as a consequence self-configuration and restart to increase Overall Equipment Effectiveness. To understand this challenge at first the state of the art of fault handling in industrial automated production systems (aPS) is discussed as a result of a case study analysis in eight companies developing aPS. In the next step, metrics to evaluate the concept of self-configuration and restart for aPS focusing on real-time capabilities, fault coverage and effort to increase fault coverage are proposed. Finally, two different lab size case studies prove the applicability of the concepts of self-configuration, restart and the proposed metrics.

Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage

Test generation procedures for n -detection test sets improve the quality of a test set by adding tests that increase the numbers of detections of target faults. A different approach to n-detection test generation increases the numbers of detections of target faults within the bounds of the number of tests of a single-detection test set. Multicycle tests provide the flexibility of improving the quality of a test set by increasing the number of clock cycles in each test, without increasing the number of tests. Improved test quality is thus achieved with limited increases in test application time and test data volume due to the larger numbers of clock cycles in each test. This paper describes a procedure that starts from a compact one-detection single-cycle test set for single stuck-at faults and produces a multicycle test set with the same number of tests, but increased numbers of clock cycles and improved test quality. The procedure uses only one-detection fault simulation of single stuck-at faults. A similar procedure is applied starting from a two-cycle test set and considering transition faults. The procedures produce tests with constant primary input vectors to accommodate tester limitations.

Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application

ATPG based on Boolean satisfiability (SAT) turned out to be a robust alternative to classical structural automatic test pattern generation (ATPG) algorithms performing very well especially for hard-to-detect faults but suffer from the overhead for easy-to-detect faults. In this letter, we propose new efficient data structures and methodologies for SAT-based ATPG. The novel incremental SAT solving technique dynamic clause activation which makes use of structural information using dedicated data structures forms the core of a new flexible SAT-based ATPG approach. Experimental results on large industrial circuits show a significant performance gain and a removal of the limitations. At the same time, the robustness of SAT-based ATPG can even be strengthened resulting in very high fault efficiency and increased fault coverage for transition faults.

Analysis of multibackground memory testing techniques

Analysis of multibackground memory testing techniquesMarch tests are widely used in the process of RAM testing. This family of tests is very efficient in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault model—such as pattern sensitive faults—their efficiency is not sufficient. Therefore we have to use other techniques to increase fault coverage for complex faults. Multibackground memory testing is one of such techniques. In this case a selected March test is run many times. Each time it is run with new initial conditions. One of the conditions which we can change is the initial memory background. In this paper we compare the efficiency of multibackground tests based on four different algorithms of background generation.

Evolutionary derivation of optimal test sets for neural network based analog and mixed signal circuits fault diagnosis approach

Testing issues are becoming more and more important with the quick development of both digital and analog circuit industry. In this paper, we study the utilization of evolutionary algorithms for optimal input vectors derivation of neural network based analog and mixed signal circuits fault diagnosis approach and compare the results with normal method. We have introduced a new procedure which uses the n-detection test set concept and selects the input samples in a way that for each case of fault injection, there will be at least n sample to activate that fault. This procedure performs the optimization in two ways. The first one called speed method generates samples in a way that acceptable decision strength and lower training phase duration would be achieved. The second one called stamina method generates samples in a way that best decision strength and higher training phase duration would be achieved. Experimental results demonstrate that the obtained input voltages yields fault diagnosis with increased fault coverage and high decision strength.

Ball grid array (BGA) solder joint intermittency real-time detection

This paper presents test results and specifications for SJ BIST (solder joint built-in-self-test), an innovative sensing method for detecting faults in solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well known that fractured solder joints typically maintain sufficient electrical contact to operate correctly for long periods of time. Subsequently, the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods of stress, causing incorrect FPGA signals. SJ BIST detects faults at least as low as 100 Ω with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock – guaranteed detection is two clock periods. SJ BIST correctly detects and reports instances of high-resistance with no false alarms: test results are shown in this paper. Being able to detect solder-joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance.

Minimization of Linear Dependencies Through the Use of Phase Shifters

Two-dimensional scan design with a linear test pattern generator is a practical built-in self-test technique, but it suffers from linear dependencies, which reduce the fault coverage. To alleviate this problem, networks of xor gates known as phase shifters can be employed. Current techniques based on the empirical criterion of imposing large phase shift differences (channel separations) between successive scan chains cannot adequately remove the dependencies. In this paper, we present a method that addresses explicitly the minimization of linear dependencies through appropriate selection of phase shift values. The method is based on the criterion of minimizing the linear dependencies in each cone of the circuit under test, and is applicable to any type of linear test pattern generator, be it linear feedback shift register of the external- xor or internal-xor type, cellular automaton, etc. Experimental results demonstrate the effect of the approach in increasing fault coverage.

Optimisation of the stress distribution in ceramic hip joint balls by implementation of biological growth

This paper presents test results and specifications for SJ BIST (solder joint built-in-self-test), an innovative sensing method for detecting faults in solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well known that fractured solder joints typically maintain sufficient electrical contact to operate correctly for long periods of time. Subsequently, the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods of stress, causing incorrect FPGA signals. SJ BIST detects faults at least as low as 100 Ω with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock – guaranteed detection is two clock periods. SJ BIST correctly detects and reports instances of high-resistance with no false alarms: test results are shown in this paper. Being able to detect solder-joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance.

Linked Faults in Random Access Memories: Concept, Fault Models, Test Algorithms, and Industrial Results

The analysis of linked faults (LFs), which are faults that influence the behavior of each other, such that masking can occur, has proven to be a source for new memory tests, characterized by an increased fault coverage. However, many newly reported fault models have not been investigated from the point-of-view of LFs. This paper presents a complete analysis of LFs, based on the concept of fault primitives, such that the whole space of LFs is investigated and accounted for and validated. Some simulated defective circuits, showing linked-fault behavior, will be also presented. The paper establishes detection conditions along with new tests to detect each fault class. The tests are merged into a single test March SL detecting all considered LFs. Preliminary test results, based on Intel advanced caches, show that its fault coverage is high as compared with all other traditional tests and that it detects some unique faults; this makes March SL very attractive industrially.

New test structure for VLSI self-test: the structured test register (STR)

A new test structure which facilitates self-test in digital VLSI integrated circuits is presented. This test structure, termed the structured test register (STR), is constructed by adding some extra components to an otherwise standard BILBO. The advantages of this circuit in terms of increased fault coverage on both the functional and self-test parts of the circuit are described.

Fault detection in sequential machines with increased fault coverage

This letter develops an approach for fault detection and checking sequence design of sequential machines based on the principle of machine modification through augmentation of extra input and extra outputs, taking into consideration the case where faults occurring in a machine may cause an increase in its number of states.