Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array

Abstract

Static random access memories (SRAM) are a major constituent in high performance microprocessors and systems-on-a-chip. With scaling of technology, manufacturing process variations in SRAMs are of significant concern. SRAM cells that are marginal due to process variations suffer from stability issues where random thermal noise and random telegraph noise (RTN) become determinant in memory state. This introduces uncertainty in testing, where passing a test does not necessarily mean that SRAM is good. A marginal cell may pass testing, but fail during operation. To address this problem, we introduce a new metric for probabilistic fault coverage. We present simulation methods for measuring such coverage and propose N-detect and multilevel wordline (WL) voltage techniques to increase the detection probability of marginal cells. We demonstrate the benefit of these testing approaches on a sample SRAM array, designed in 32 nm predictive technology models. To simulate marginal cells, we oversample the tail of the process variations distribution. Transient noise simulations show that thermal noise can lead to a fault coverage loss of 20% and RTN can lead to a maximum fault coverage loss of up to 75%. N-detect technique achieves close to a 100% fault coverage at ${n}\,\, {=} 100$ for thermal noise and ${n}\,\,{=} 70$ for RTN. Multilevel WL technique requires 20–30 mV boost in WL voltage during read test to achieve near ideal fault coverage at minimal yield loss. A combination of these techniques is shown to be effective in increasing fault coverage with a tradeoff between test time and yield loss.