Abstract
This paper presents test results and specifications for SJ BIST (solder joint built-in-self-test), an innovative sensing method for detecting faults in solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well known that fractured solder joints typically maintain sufficient electrical contact to operate correctly for long periods of time. Subsequently, the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods of stress, causing incorrect FPGA signals. SJ BIST detects faults at least as low as 100 Ω with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock – guaranteed detection is two clock periods. SJ BIST correctly detects and reports instances of high-resistance with no false alarms: test results are shown in this paper. Being able to detect solder-joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance.
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