Improvement In Current Gain Research Articles

Steep subthreshold slope in nano-wire TFET using a potential well

In this paper, we investigate the effect of a potential well between the source and channel on the subthreshold swing and On-current of a nano-wire TFET. Here, we benefit from the difference between the electron affinities and the band gaps of the Si and the Ge to create a potential well. While the source and the channel are composed of Ge, we place a thin Si layer between them which results in a potential well. By employing this structure, we were able to decrease the subthreshold swing to 15.7 mV/dec and achieve a high Ion at the same time. Additionally, the peak value of the electric field in the device has been decreased by 20 percent, which means we can reduce device size with fewer undesirable effects. In the context of RF analysis, the proposed device exhibits improvements in current gain and unilateral power gain compared to conventional structures. We also examine the impact of interface traps at Ge/Si interface and gate alignment with the potential well.

Cylindrical Fresnel lens: An innovative path toward a tracking-less concentrating photovoltaics system

We here invent an implicitly new optical device - cylindrical Fresnel lenses historically used in the decades-old lighthouse concentrator to find application in the field of concentrator photovoltaic, with numerous demonstrations of exotic features in optics. The precious attribute of such a solar concentrator is its ability to grant a focal point sequence, essentially distributed over an arc at any light incidence. The other striking merit of this design is its high acceptance angle, about 60°, at hand and even up to 90°, ideally. We have applied this approach to a simplified principle-of-concept model that closely depicts the octagonal cylindrical Fresnel lens in essence. This convergence feature was evidenced in a mock-up model through optical simulation and further consolidated by electrical characteristics analysis. Specifically, the simulation affirmed that an optimal structure can attain a concentration ratio of ∼23 and an optical efficiency of ∼70%. We indeed confirmed through an outdoor experiment a 16-fold improvement of current gain, which was close to the simulation result. Of further exceptional interest in such a design is its compatibility with two mature common tracking mechanisms: daily or yearly single-axis tracking, leaving room for design compromises. This design leaves ample margins for simple and low-cost light couplers, which are advantageous in affordable concentrator photovoltaic systems. In addition, the quantitative assessment unravelled that the generated power can be enhanced 1.3× in comparison with the flat Silic panel. We describe the potential realization of the large-scale of the model, making this solar concentrator amenable to commercialization.

Impact of strained silicon on the device performance of a bipolar charge plasma transistor

In this manuscript we analyze a unique approach to improve the performance of the bipolar charge plasma transistor (BCPT) by introducing a strained Si/SixGe1−x layer as the active device region. For charge plasma realization different metal work-function electrodes are used to induce n+ and p+ regions on undoped strained silicon-on-insulator (sSOI or SixGe1−x) to realize emitter, base, and collector regions of the BCPT. Here, by using a calibrated 2-D TCAD simulation the impact of a Si mole fraction x (in SixGe1−x) on device performance metrics is investigated. The analysis demonstrates the band gap lowering with decreasing Si content or effective strain on the Si layer, and its subsequent advantages. This work reports a significant improvement in current gain, cutoff frequency, and lower collector breakdown voltage (BVCEO) for the proposed structure over the conventional device. The effect of varying temperature on the strained Si layer and its implications on the device performance is also investigated. The analysis demonstrates a fair device-level understanding and exhibits the immense potential of the SixGe1−x material as the device layer. In addition to this, using extensive 2-D mixed-mode TCAD simulation, a considerable improvement in switching transient times are also observed compared to its conventional counterpart.

Improvement of Current Gain and Breakdown Voltage in 4H-SiC BJTs Employing High-k Dielectric as an Interfacial Layer

This paper proposes a new structure of 4H-SiC bipolar junction transistor, which can both achieve high current gain and high open base breakdown voltage. By introducing a groove type of metal-high k dielectric-silicon carbide (MIS) structure into the active region along the base-emitter sidewall which is formed with the process of isolation etching, a large electric field appears at the interface between high-k dielectric and bulk material by analyzing the potential distribution in forward mode, thus accelerating the electron transport. Based on a doping concentration of 4×1017cm-3 and thickness of 0.6um base region, current gain of as high as 191 is obtained using TCAD simulation, and that is almost double of the conventional structure in the same simulation setup. Furthermore, a field plate structure is composed combined with the base contact metal simultaneously, and the open base breakdown voltage is obviously increased from 634V to 948V with a 6μm-thick n-SiC collector (Nd=3×1015cm-3).

A high performance charge plasma PN-Schottky collector transistor on silicon-on-insulator

In this paper, we propose a new high performance PN-Schottky collector (PN-SC) lateral bipolar junction transistor (BJT) on silicon-on-insulator (SOI). The proposed device addresses the problem of poor speed of conventional lateral PNP-BJT device by using a Schottky collector. Further, it does not use the conventional ways of ion implantation/diffusion to realize n and p type doped region. However, it uses metal electrodes of different work functions to create n and p type charge plasma in an undoped silicon film. The simulation study of the proposed lateral PN-SC bipolar charge plasma transistor on SOI (PN-SC-BCPT) device has shown a significant improvement in current gain (β), cutoff frequency (fT) and switching performance in comparison to conventional PNP-BJT and PNP-bipolar charge plasma transistor (PNP-BCPT) devices. A significantly high β is obtained in the proposed PN-SC-BCPT (∼2100) in comparison to PNP-BCPT (∼1450) and the conventional BJT (∼9) devices, respectively. It has been observed that there is 89.56% and 153.5% increase in fT for the proposed PN-SC-BCPT device (2.18 GHz) in comparison to conventional PNP-BJT (1.15 GHz) and PNP-BCPT (0.86 GHz) devices, respectively. Further, reductions of 24.6% and 15.4% in switching ON-delay and 66% and 30.76% in switching OFF-delay have been achieved in the proposed device based inverters in comparison to PNP-BCPT and the conventional BJT devices based inverters, respectively. Furthermore, the proposed device does not face doping related issues and the requirement of high temperature processing is absent.

AlGaN/SiC Heterojunction Bipolar Transistors Featuring AlN/GaN Short-Period Superlattice Emitter

Growth and electrical characterization of aluminum gallium nitride (AlGaN)/SiC heterojunction bipolar transistors (HBTs) featuring AlN/GaN short-period superlattice as a quasi-AlGaN emitter are presented. The AlN/GaN superlattice emitter was grown by molecular beam epitaxy on off-axis SiC, which showed adequate structural and electronic properties as the emitter of the HBTs. We investigated the impact of Al composition in the emitter on the transport characteristics and current gain of the HBTs. Using Al composition of over 0.5, we achieved type-I band alignment in AlGaN/SiC, and suppressed the tunneling current via interface traps, resulting in an improved current gain of up to 2.7. Toward further improvement of current gain, we also investigated the effect of n-SiC spacer between n-AlGaN and p-SiC and p-SiC base width. Using 200-nm-thick n-SiC spacer and 250-nm-thick p-SiC base layer, we achieved an improved current gain of 13 owing to the reduced interface and bulk recombination.

Improved Current Gain in 4H-SiC BJTs Passivated with Deposited Oxides Followed by Nitridation

We report the improvement of current gain in 4H-SiC bipolar junction transistors (BJTs) by using deposited oxides as a surface passivation layer. Various post-deposition annealing processes were investigated. We successfully demonstrated SiC BJTs with a high current gain (β) of 86 using deposited oxides annealed in NO. This is 70% higher current gain compared with that of BJTs with the same structure with conventional thermally-grown oxides.

Improvement of Current Gain in 4H-SiC BJTs by Surface Passivation With Deposited Oxides Nitrided in $\hbox{N}_{2}\hbox{O}$ or NO

We report the improvement of current gain in 4H-SiC bipolar junction transistors (BJTs) by utilizing deposited oxides as a surface passivation layer. Various post deposition annealing processes, including annealing ambient (N2, N2O, and NO) and annealing time, were investigated. We successfully demonstrate SiC BJTs with high current gains (β) of 73 and 102 using deposited oxides annealed in N2O and NO, respectively, whereas BJTs having conventional thermally grown oxides showed a current gain of 50.

Extrinsic Base Surface Passivation in High Speed “Type-II" GaAsSb/InP DHBTs Using an InGaAsP Ledge Structure

Type-II GaAsSb/InP DHBTs with selectively-etched InGaAsP ledge structures are fabricated and characterized for the first time. The novel InGaAsP/GaAsSb/InP DHBTs with a 20 nm lattice-matched GaAsSb base and a 75 nm InP collector have a dc current gain improvement by a factor of 2 and a cutoff frequency fT of 190 GHz. The InGaAsP ledge design provides a simple but effective approach to suppress the extrinsic base surface recombination and enable GaAsSb/InP DHBTs to further increase the operating frequencies and integration levels for millimeter wave applications.

Improvement of Current Gain with Etched Extrinsic Base Regions of Triple Ion Implanted SiC BJT

In this paper, we demonstrate triple ion implanted 4H-SiC bipolar junction transistor (BJT) with etched extrinsic base regions. At the result of etching extrinsic base regions by mask of contact metals, maximum common emitter current gain was improved from 0.7 to 1.6.

Analytical Model and Current Gain Enhancement of Polysilicon-Emitter Contact Bipolar Transistors

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents an analytical model that simulates the current gain improvement of polysilicon-emitter bipolar transistors based on the effective recombination velocity method. The theoretical framework developed in this paper incorporates the 2-D structure effect of the polysilicon layer with columnar grain boundary, tunneling processes of holes through polysilicon/silicon interface oxide layer, and nonuniform doping concentration and bulk recombination effects in the single-crystal emitter. The study goes on to derive an analytical expression for the base current density from which the analytical expression of the current gain was then derived. The effect of oxide breakup, at the polysilicon/silicon interface, on current gain was also considered. The dependence of the current gain on temperature was analyzed numerically; the results are in good agreement with experimental data. The approach outlined in this paper allows one to avoid many of the unnecessary simplifications inherent in previous works and to clearly assess the relevance of each physical mechanism. </para>

Effects of arsenic mole fraction x on the gain characteristics of type-II InP/GaAsxSb1−x DHBTs

The static gain characteristics of N–p–N InP/GaAsxSb1−x/InP double heterojunction bipolar transistors (DHBTs) were studied as a function of the base arsenic (As) mole fraction x. Compared to the devices with a lattice-matched base (x=0.51), a current gain improvement largely arising from a base current reduction is observed in DHBTs with higher As base mole fractions (and consequently a reduced type-II conduction band discontinuity ΔEC at the emitter-base heterojunction). Both the surface periphery and the intrinsic recombination currents decrease markedly as the base arsenic concentration increases. The present work therefore unambiguously demonstrates that the emitter type-II conduction band discontinuity between the InP emitter and the GaAsxSb1−x base enhances the undesirable emitter size effects (ESEs) and increases intrinsic recombination currents directly under the emitter contact.

Surface passivation oxide effects on the current gain of 4H-SiC bipolar junction transistors

Effects of surface recombination on the common emitter current gain have been studied in 4H-silicon carbide (SiC) bipolar junction transistors (BJTs) with passivation formed by conventional dry oxidation and with passivation formed by dry oxidation in nitrous oxide (N2O) ambient. A gradual reduction of the current gain was found after removal of the passivation oxide followed by air exposure. Comparison of the measurement results for two different passivated BJTs indicates that the BJTs with passivation by dry oxidation in nitrous oxide (N2O) ambient show a half order of magnitude reduction of base current, resulting in a half order of magnitude increase of current gain at low currents. This improvement of current gain is attributed to reduced surface recombination caused by reduced interface trap densities at the base-emitter junction sidewall.

Improvement of current gain of C-doped GaAsSb-base heterojunction bipolar transistors by using an InAlP emitter

Large conduction band edge discontinuity (ΔEc) at the emitter/base interface in InP∕GaAs0.51Sb0.49∕InP heterojunction bipolar transistor (HBT) is one of the possible reasons that the recombination process in the emitter/base depletion region dominates the characteristics of this HBT. We fabricate an InAlP emitter∕GaAs0.51Sb0.49base∕InP collector HBT for reducing the ΔEc at the emitter/base interface. It is demonstrated that a HBT with an InAlP emitter shows a relatively lower recombination current than one with an InP emitter, resulting in the higher current gain. It is also found that the decrease of recombination current depends on the Al content of InAlP emitter. Additionally, the ideality factor of the emitter-base current is smallest at the Al content of 0.15 in the InAlP emitter. These results indicate that using an InAlP emitter is effective for improving the current gain of GaAsSb-base HBTs.

MOCVD‐Grown InGa/GaAs Emitter Delta Doping Heterojunction Bipolar Transistors

The influence of delta doping sheet at base‐emitter (BE) junction for an InGaP/GaAs heterojunction bipolar transistor (HBT) with a 75Å undoped spacer layer is investigated. A common emitter current gain of 235, an offset voltage as small as 50mV and an Ic ideal factor of 1.01 are obtained, respectively. The use of delta doping sheet at BE junction results in a high gain and low offset voltage HBT. The improvement of current gain and offset voltage may be attributed to the reduction of BE potential spike by introducing a delta doping layer even without the BE junction passivation.

Study of In0.49Ga0.51P/GaAs/In0.49Ga0.51P doubleδ-doped heterojunction bipolar transistor

A lattice-matched In0.49Ga0.51P/GaAs/In0.49Ga0.51P doubleδ -doped heterojunction bipolar transistor, prepared by low-pressure metal organic chemical vapor deposition (LP-MOCVD), is fabricated successfully and reported. Due to the insertion of δ -doped sheets and setback layers both at base–emitter (B–E) and base–collector (B–C) heterojunctions, the potential spikes are suppressed significantly. In addition, the electron blocking effect is removed and a dramatic improvement of current gain is obtained. A modified Ebers–Moll model is employed to study and analyse the device performances. The experimental results show that the common-emitter current gain over 210 at the collector current of 35 mA and an offset voltageΔVCE smaller than 50 mV are obtained. Also, a lower knee-shaped voltage of 1.4 V at the collector current of 40 mA is observed. These results indicate that the device studied is a good candidate for high-speed and high-power circuit applications.

A high sensitivity lead-titanate (PbTiO3) pyroelectric thin-film infrared sensor with temperature isolation improvement structure

An infrared (IR) sensor with the lead-titanate (PbTiO/sub 3/) thin-film using the technology of micro-electromechanical system to achieve a better thermal isolation structure has been fabricated and developed, The major IR-sensing part on the cantilever beam with dimensions of 200/spl times/100/spl times/2 /spl mu/m/sup 3/ consists of a 500 /spl Aring/ PbTiO/sub 3/ layer deposited by RF sputtering, and an evaporated bismuth (Bi) layer. This thermal isolation improved structure exhibits a much superior performance to that of a traditional IR-sensing bulk structure on the experimental results, which show a 200% and 300% improvement in current gain under the incident optical power 500 /spl mu/W and 6 V applied bias at room temperature and 77 K, respectively,.

High current gain, low offset voltage heterostructure emitter bipolar transistors

Heterostructure Emitter Bipolar Transistors (HEBT's) were fabricated with improved characteristics by employing the emitter edge-thinning technique. Optimum design for the n-GaAs emitter and the ledge thickness were used to remove the potential spike and to prevent ledge conduction simultaneously. Current gains as high as 720, which is the highest current gain ever reported for HEBT's, and offset voltages down to 70 mV were obtained. Very large improvement in current gain, especially at low collector current, was obtained by using the emitter edge-thinning technique.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Bipolar transistors for low noise, low temperature electronics

In silicon MOS technology, 1/ f noise increases as the device geometry shrinks, making MOS field effect transistors unacceptable for low noise, high density analog applications. While bipolar technology is available for such applications at room temperature, it was not practical until recently for cryogenic operation because of unacceptably low current gain at low temperatures. This paper reports the noise properties and conduction characteristics of bipolar transistors at cryogenic temperatures. These devices were fabricated with high density, polyemitter bipolar processing technology, and respectable current gains greater than 500 down to 40 K can be obtained. Noise measurements at low temperatures show that 1/ f noise is an order of magnitude smaller than in MOS devices of equal area. White noise also decreases at low temperatures due to a decrease in series resistances and an improvement in current gain. These results seem to open possibilities for high density cryogenic bipolar technology for low noise, low temperature electronics.

Si/Ge0.3Si0.7/Si heterojunction bipolar transistor made with Si molecular beam epitaxy

GexSi1−x heterobase n-p-n heterojunction bipolar transistor structure has been grown completely by Si molecular beam epitaxy for the first time. A collector-top type design was adopted. The 3000 Å p-type Ge0.3Si0.7 heterobase layer with 5×1019 cm−3 doping level was grown on an emitter layer which was an arsenic highly doped substrate (7×1019 cm−3), followed by a 5000 Å n-type Si collector layer with 7×1017 cm−3 doping level. Low-temperature device processes under 650 °C were used to avoid thermal diffusion of impurities. Common-emitter current gain hFE with a 100-μm-diam emitter was 15 at 2×104 A/cm2 collector current density. Compared with a usual Si-base bipolar transistor of the same size and doping level, an improvement in current gain was observed. Furthermore, GexSi1−x/Si (x=0.1–0.4) p-n junction interfaces were investigated by current-voltage and capacitance-voltage measurements and transmission electron microscopy observation.