Impact of strained silicon on the device performance of a bipolar charge plasma transistor

Abstract

In this manuscript we analyze a unique approach to improve the performance of the bipolar charge plasma transistor (BCPT) by introducing a strained Si/SixGe1−x layer as the active device region. For charge plasma realization different metal work-function electrodes are used to induce n+ and p+ regions on undoped strained silicon-on-insulator (sSOI or SixGe1−x) to realize emitter, base, and collector regions of the BCPT. Here, by using a calibrated 2-D TCAD simulation the impact of a Si mole fraction x (in SixGe1−x) on device performance metrics is investigated. The analysis demonstrates the band gap lowering with decreasing Si content or effective strain on the Si layer, and its subsequent advantages. This work reports a significant improvement in current gain, cutoff frequency, and lower collector breakdown voltage (BVCEO) for the proposed structure over the conventional device. The effect of varying temperature on the strained Si layer and its implications on the device performance is also investigated. The analysis demonstrates a fair device-level understanding and exhibits the immense potential of the SixGe1−x material as the device layer. In addition to this, using extensive 2-D mixed-mode TCAD simulation, a considerable improvement in switching transient times are also observed compared to its conventional counterpart.