Impedance Field Method Research Articles

Spacer effects on the performance of MoTe2/MoSe2 and MoTe2/WSe2 heterostructure double gate MOSFET

In this work, the spacer effects (both low and high-k) on the dc and noise characteristics of heterostructure molybdenum ditelluride (MoTe2/MoSe2 and MoTe2/WSe2) double gate (DG) MOSFET is analyzed. To study the device characteristics, a hybrid methodology that uses both QuantumWise ATK and Sentaurus TCAD tool is used. The performance metrics of the device such as on-current (Ion), Ion/Ioff ratio, subthreshold swing (SS), threshold voltage are obtained. The noise performance of the device is also studied (with/without spacer) using impedance field method. Noise parameters such as noise power spectral density (SID) and noise figure (function of both frequency and bias) has also been simulated and noise components such as G-R noise, flicker noise and white noise are obtained. The simulation results shows that the introduction of spacer material enhances the dc performance of the device and influences its noise characteristics.

Variability analysis of the epitaxial layer TFET due to gate work function variation, random dopant fluctuation, and oxide thickness fluctuation using the statistical impedance field method

In this paper, a comparative study on process variability considering work function variation (WFV), random dopant fluctuation (RDF), and oxide thickness fluctuation (OTF) in epitaxial layer tunnel field effect transistor (TFET) with SiGe source (SiGe-ETLTFET) is statistically analyzed using impedance field method (IFM) in Santaurus TCAD tool. Effect of different grain sizes of the gate metal and other device parameter scaling on the variability source are investigated by evaluating the standard deviation of threshold voltage (V th), on current (I ON), and off current (I OFF). At smaller AverageGrainSize, the dispersions in electrical parameters are close to normal, whereas for large AverageGrainSize dispersion increases and deviates from the normal distribution. Compared to RDF and WFV, OTF is not a significant cause of variability in SiGe-ETLTFET. It is found that RDF is the most sensitive variability source while device scaling is concerned. Moreover, L ov scaling causes the most acute fluctuation of electrical parameters for all considered variability sources. The slope of the Pelgrom plot, A VT, of SiGe-ETLTFET considering all variability sources, is smaller than the already reported values for the FinFET and MOSFET.

Impact of process variability in junctionless FinFETs due to random dopant fluctuation, gate work function variation, and oxide thickness variation

In this paper, process variability such as random dopant fluctuation (RDF), work function variation (WFV), and oxide thickness variation (OTV) in 14 nm node junctionless (JL) FinFETs is investigated using the impedance field method (IFM). Effects of doping concentration, gate metal grain-related parameters, and device parameter scaling on RDF, WFV, and OTV induced variability are studied using the standard deviations of threshold voltage (σVth) and subthreshold slope (σSsub). As a result, we find that a relatively low doping concentration helps alleviate process variability. As average grain size increases, different mechanisms of σVth and σSsub degradation are analyzed for WFV and OTV induced variability. Compared to WFV and OTV, RDF is revealed as the most significant source of variability as devices scale down. It is observed that fin width (Wfin) and oxide thickness (tox) scaling leads to the reduction of RDF induced variability, whereas channel length (L) and fin height (Hfin) scaling results in aggravation of RDF, WFV, and OTV induced variability.

1/${f}^{\gamma}$ Low Frequency Noise Model for Buried Channel MOSFET

The Low Frequency Noise (LFN) in MOSFETs is critical to Signal-to-Noise Ratio (SNR) demanding circuits. Buried Channel (BC) MOSFETs are commonly used as the source-follower transistors for CCDs and CMOS image sensors (CIS) for lower LFN. It is essential to understand the BC MOSFETs noise mechanism based on trap parameters with different transistor biasing conditions. In this paper, we have designed and fabricated deep BC MOSFETs in a CIS-compatible process with 5 V rating. The ${1}/{f^{\gamma }}$ LFN is found due to non-uniform space and energy distributed oxide traps. To comprehensively explain the BC MOSFETs noise spectrum, we developed a LFN model based on the Shockley–Read–Hall (SRH) theory with WKB tunneling approximation. This is the first time that the ${ 1}/{f^{\gamma }}$ LFN spectrum of BC MOSFET has been numerically analyzed and modeled. The Random Telegraph Signal (RTS) amplitudes of each oxide traps are extracted efficiently with an Impedance Field Method (IFM). Our new model counts the noise contribution from each discretized oxide trap in oxide mesh grids. Experiments verify that the new model matches well the noise power spectrum from 10 to 10k Hz with various gate biasing conditions from accumulation to weak inversion.

Improved statistical variability and delay performance with junctionless inserted oxide FinFET

Junctionless inserted oxide FinFET (JL-iFinFET) is presented, its performance metrics are quantified and compared with JL-FinFET and JL-Stacked-Nanowire-FET (JL-SNWFET) respectively for the same foot-print on the wafer. The Random-Dopant-Fluctuation (RDF) and Metal-Gate-Granularity (MGG) are major variability sources in nano-transistors. Impedance Field Method is used to analyze the statistical variability performance of all three structures caused by RDF and MGG. The result shows JL-SNWFET provides superior DC figure-of-merits and 40% less statistical variability than JL-FinFET with a 10% increase in delay and considerable increase in fabrication complexity. The JL-iFinFET offers 30% lesser process-induced threshold voltage and on-current variations compare to JL-FinFET, without deteriorating delay and RF metrics due to its superior electrostatic control over the channel and multi-channel configuration. Fabrication of JL-iFinFET is also possible without adding much complexity in FinFET process it can be a major contender for continued scaling with JL-Transistors (JLTs).

Analysis and Modeling of Current Mismatch in Laterally Nonuniform MOSFETs

We present an analytical modeling approach for drain current ( ${I}_{D}$ ) mismatch in lateral nonuniformly doped (NUD) MOSFETs. The model uses the carrier number fluctuation theory to include the effect of random dopant fluctuations (RDFs) on inversion charge fluctuation (ICF) in different operating regions. Our analysis shows that the conventional models for uniformly doped device underestimate the ${I}_{D}$ mismatch by one-to-two orders of magnitude at low gate voltages in NUD devices. We have also considered the effect of RDF on mobility fluctuation (MF), which shows its significant role in strong inversion (SI). To investigate the physical mechanism leading to such a behavior, extensive technology computer-aided design simulations are performed for various conditions of bias, doping profiles, and temperature. Using the impedance field method to calculate the relative contributions of RDF to ICF and MF, we show that our model can successfully capture the drain current mismatch across subthreshold to SI in the NUD device.

Analysis and Modeling of Temperature and Bias Dependence of Current Mismatch in Halo-Implanted MOSFETs

We present an analytical model that accurately captures anomalous matching characteristics of drain current in a halo-implanted MOSFET across bias, geometry, and temperature. It is shown that the variation in drain current in different gate bias regimes results from the random-dopant fluctuations (RDFs) in different spatial regions across the channel of the device with nonuniform channel doping. Such effects cannot be captured by existing compact models. Using the impedance field method to calculate the relative contributions of the RDF in the higher doped halo region and the lower doped channel region, we demonstrate, for the first time, an analytical model that can successfully capture the drain current mismatch from subthreshold to strong inversion. We also report for the first time the unique temperature dependence of matching of the drain current in halo-implanted devices and propose a model to capture this behavior. The model is validated using extensive technology computer-aided design analysis and experimental data and is can be extended to the framework of the industry standard BSIM-BULK (formerly BSIM6) MOS model.

OFF-State Leakage and Performance Variations Associated With Germanium Preamorphization Implant in Silicon–Germanium Channel pFET

Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon–germanium (SiGe) for p-type field effect transistor (pFET) at 32 nm and beyond are useful because of higher mobility and lower threshold voltage ( $\text{V}_{T}$ ) but suffer from higher gate-induced drain leakage (GIDL) and could be a source of additional variability. In this paper, experimental results, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe pFET process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random GIDL and performance variations. This is primarily due to random dopant position fluctuations in the extension region for off-state leakage ( ${I}_{ \mathrm{\scriptscriptstyle OFF}} $ ) variability and in the halo region at the drain sidewall for $\text{V}_{T}$ variability. However, the increase in random variability without Ge PAI reduces for lower supply voltages and, thus, offers advantages of reduced GIDL with the same electrostatics, lower systematic variations, and similar ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ random variability for scaled voltages.

3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes

Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for realization of advanced CMOS technology nodes. Due to small nanowire dimensions, NWFETs are vulnerable to the impact of process-induced random local variations, such as the line edge roughness (LER) and random dopant fluctuation (RDF). NWFETs have three different device modes, namely, the inversion mode (IM), the accumulation mode (AM), and the junctionless (JL) mode. In this paper, a 3-D quasi-atomistic LER model is used for the analysis of LER-induced mismatch in JL, IM, and AM NWFETs. We have also compared the impact of 3-D LER with that of 2-D LER. In addition, another emerging simulation methodology known as statistical impedance field method is utilized to analyze the impact of RDF on the three flavors of NWFETs. We show that JL NWFETs have much higher mismatch due to both LER and RDF than their IM and AM NWFET counterparts with otherwise identical device structure.

Influence of Dopants Profile on Random Dopant Fluctuation and Optimization for Bulk FinFET

Influence of dopant profile on random dopant fluctuation (RDF) for bulk FinFET is investigated by impedance field method, which reveals that center of fin is the most sensitive position. The dopant in fin is inevitable by conventional implanted punch thought stop layer (PTSL), which results in severe variation of threshold voltage. The subfin doping technique (SDT) can enable better optimization of dopants profile in a proper annealing condition. To further reduce the influence of RDF, a method called charged sidewall doping (CSD) is proposed, which completely avoids the introduction of dopants in fin and can be achieved through a sidewall layer with charge.

Total Ionizing Dose, Random Dopant Fluctuations, and its combined effect in the 45 nm PDSOI node

Total Ionizing Dose and Random Dopant Fluctuation simulations in 45nm Partially Depleted Silicon-on-Insulator nMOSFETs are presented. Calibration is done according to the commercial IBM 45nm technology node. The importance of the bottom corner parasitic transistor to the Total Ionizing Dose response is shown with the use of ultra shallow junctions. Simulation of irradiation in two-dimensional slices of the device reveal that the majority of the charge is trapped around the silicon film and at the bottom of the Buried OXide in the case of a positive gate bias. Random Dopant Fluctuations are examined using the Sano and the Impedance Field Method. The simulation results of the two methods are in good agreement. Dopant fluctuations do not produce significant response variation pre-irradiation, but they affect post-irradiation results introducing statistical deviations and aggravating Total Ionizing Dose effects. This effect is more pronounced during weak inversion of the parasitic transistor.

Analysis and modeling of flicker noise in lateral asymmetric channel MOSFETs

In this paper, flicker noise behavior of lateral non-uniformly doped MOSFET is studied using impedance field method. Our study shows that Klaassen Prins (KP) method, which forms the basis of noise model in MOSFETs, underestimates flicker noise in such devices. The same KP method overestimates thermal noise by 2–3 orders of magnitude in similar devices as demonstrated in Roy et al. (2007). This apparent discrepancy between thermal and flicker noise behavior lies in origin of these noises, which leads to opposite trend of local noise power spectral density vs doping. We have modeled the physics behind such behavior, which also explain the trends observed in the measurements (Agarwal et al., 2015).

General Geometric Fluctuation Modeling for Device Variability Analysis

The authors propose a new modeling approach based on the impedance field method (IFM) to analyze the general geometric variations in device simulations. Compared with the direct modeling of multiple variational devices, the proposed geometric variation (GV) model shows a better efficiency thanks to its IFM based nature. Compared with the existing random geometric fluctuation (RGF) model where the noise sources are limited to the interfaces, the present GV model provides better accuracy and wider application areas as it transforms the geometric variation into global mesh deformation and computes the noise sources induced by the geometric variation in the whole simulation domain. GV model also provides great insights into the device by providing the effective noise sources, equation-wise contributions, and sensitivity maps that are useful for device characterization and optimization.

Investigation of the RTN amplitude statistics of nanoscale MOS devices by the statistical impedance field method

This paper presents a numerical investigation of the random telegraph noise amplitude in nanoscale MOS devices based on the statistical impedance field method. This method allows a strong reduction of the computational burdens required for the calculation of the amplitude statistics with respect to conventional Monte Carlo models based on the numerical implementation of microscopic differences on the simulated device structure, allowing the exploration of lower probability levels. Despite a rather good estimation of the amplitude statistics, however, the method results in relevant inaccuracies when looking at the single Monte Carlo samples, due to the linear approximations involved.

Investigation of the Statistical Variability of Static Noise Margins of SRAM Cells Using the Statistical Impedance Field Method

The statistical variability of the static noise margin of a six-transistor bulk complementary metal-oxide-semiconductor static random access memory (SRAM) cell due to random doping fluctuations (RDFs) is investigated via 3-D technology computer-aided design simulations. The SRAM cell is created through 3-D process simulations of the entire cell as a single structure. The process flow is based on a typical 32-nm technology. The effects of RDFs on the cell performance are investigated using the highly efficient statistical impedance field method.

Analytical and Numerical Model Confrontation for Transfer Impedance Extraction in Three-Dimensional Radio Frequency Circuits

3D chip stacking is considered known to overcome conventional 2D-IC issues, using through silicon vias to ensure vertical signal transmission. From any point source, embedded or not, we calculate the impedance spread out; our ultimate goal will to study substrate noise via impedance field method. For this, our approach is twofold: a compact Green function or a Transmission Line Model over a multi-layered substrate is derived by solving Poisson’s equation analytically. The Discrete Cosine Transform (DCT) and its variations are used for rapid evaluation. Using this technique, the substrate coupling and loss in IC’s can be analyzed. We implement our algorithm in MATLAB; it permits to extract impedances between any pair of embedded contacts. Comparisons are performed using finite element methods.

Comparative Simulation Study of the Different Sources of Statistical Variability in Contemporary Floating-Gate Nonvolatile Memory

For the first time, a comprehensive comparative study of the impact of different sources of statistical variability in nonvolatile memory (NVM) has been carried out using the 3-D numerical simulation of large statistical ensembles and approaches based on the impedance-field method. Results of the threshold voltage variability in a template 32-nm floating-gate NVM subject to random discrete dopants (RDD), line edge roughness, oxide thickness fluctuations, polysilicon granularity, and interface trapped charge (ITC) are presented. The relative impact of each source of statistical variability has been highlighted, with RDD being identified as the dominant source and ITC as the next most dominant source. Based on the simulation of statistical samples of 1000 microscopically different devices, the shape and spread of the statistical distribution associated with each individual and combined sources of variability have been found to significantly be different from a normal distribution, particularly within the tails that may have significant implications for design and yield. Finally, an ensemble of 59 000 devices is used to characterize the combined impact of all sources of variability.

Effect of the gate scaling on the analogue performance of s-Si CMOS devices

In this contribution, we present a detailed study of the analogue performance of deep submicron strained n-channel Si/SiGe (s-Si) MOSFETs. The study was carried out using a 2D device simulator based on the hydrodynamic model and the impedance field method to self-consistently obtain the current noise at the device's terminals. The analysis focused on the possible benefits of the gate scaling on the ac and noise performance of the transistor for low-power applications while keeping constant the oxide thickness equal to 2 nm to guarantee negligible level of the gate tunnel current. For a drain to source bias of 50 mV, it was found that a pure scaling of the transistor's gate length under 32 nm is detrimental for subthreshold operation in terms of the subthreshold slope (S) and transconductance (gm) but would lead to reasonably low values of the minimum noise figure (NFmin). For the sake of comparison, SOI MOSFETs with the same layout and operating under the same conditions were simulated. The SOI MOSFETs showed better immunity against the gate scaling in terms of S than the s-Si MOSFETs, but lower values of gm and a higher value of NFmin at the same level of the drain current. Finally, the devices have been studied in the saturation region for a drain to source bias of 1 V. In this region, it was found that the dependence of the current level SOI or s-Si MOSFET may outperform its counterparts.

A new analytical high frequency noise parameter model for AlGaN/GaN HEMT

In this paper, we propose a simple analytical high frequency noise model for AlGaN/GaN HEMT including the effect of gate leakage current. Based on the DC and CV model proposed by our group recently, the expression for drain thermal noise current is derived using the impedance field method (IFM). Using the steady-state Nyquist theorem for multiterminal devices [1], the induced-gate noise is also calculated simply and explicitly. Also, from the comparison between various measured noise results and our simulation results, the validity of our model is clearly verified.

Electronic, optical and thermal excitation of plasma waves in HEMTs: A theoretical study

We investigate the influence of collective plasma modes in a field-effect transistor channel under different excitations and biasing conditions. First, we study the case of a device externally-excited by a harmonic optical beating or an electronic excitation and current-driven at the drain. The harmonic and continuous responses of the transistor are calculated using a pseudo-two-dimensional hydrodynamic approach. They show sharp resonances related to the first odd plasma modes, whose frequencies and amplitudes can be modified by playing on the drain bias. Then, through the generalized impedance-field method we calculate also the spectral density of drain voltage fluctuations in the absence of external excitations. Also these noise spectra exhibit peaks corresponding to the odd plasma modes.