Effect of the gate scaling on the analogue performance of s-Si CMOS devices

Abstract

In this contribution, we present a detailed study of the analogue performance of deep submicron strained n-channel Si/SiGe (s-Si) MOSFETs. The study was carried out using a 2D device simulator based on the hydrodynamic model and the impedance field method to self-consistently obtain the current noise at the device's terminals. The analysis focused on the possible benefits of the gate scaling on the ac and noise performance of the transistor for low-power applications while keeping constant the oxide thickness equal to 2 nm to guarantee negligible level of the gate tunnel current. For a drain to source bias of 50 mV, it was found that a pure scaling of the transistor's gate length under 32 nm is detrimental for subthreshold operation in terms of the subthreshold slope (S) and transconductance (gm) but would lead to reasonably low values of the minimum noise figure (NFmin). For the sake of comparison, SOI MOSFETs with the same layout and operating under the same conditions were simulated. The SOI MOSFETs showed better immunity against the gate scaling in terms of S than the s-Si MOSFETs, but lower values of gm and a higher value of NFmin at the same level of the drain current. Finally, the devices have been studied in the saturation region for a drain to source bias of 1 V. In this region, it was found that the dependence of the current level SOI or s-Si MOSFET may outperform its counterparts.