Abstract
The Low Frequency Noise (LFN) in MOSFETs is critical to Signal-to-Noise Ratio (SNR) demanding circuits. Buried Channel (BC) MOSFETs are commonly used as the source-follower transistors for CCDs and CMOS image sensors (CIS) for lower LFN. It is essential to understand the BC MOSFETs noise mechanism based on trap parameters with different transistor biasing conditions. In this paper, we have designed and fabricated deep BC MOSFETs in a CIS-compatible process with 5 V rating. The ${1}/{f^{\gamma }}$ LFN is found due to non-uniform space and energy distributed oxide traps. To comprehensively explain the BC MOSFETs noise spectrum, we developed a LFN model based on the Shockley–Read–Hall (SRH) theory with WKB tunneling approximation. This is the first time that the ${ 1}/{f^{\gamma }}$ LFN spectrum of BC MOSFET has been numerically analyzed and modeled. The Random Telegraph Signal (RTS) amplitudes of each oxide traps are extracted efficiently with an Impedance Field Method (IFM). Our new model counts the noise contribution from each discretized oxide trap in oxide mesh grids. Experiments verify that the new model matches well the noise power spectrum from 10 to 10k Hz with various gate biasing conditions from accumulation to weak inversion.
Highlights
CMOS technology scaling enables high density IC integration and fast transistor operation
We introduce an Low Frequency Noise (LFN) model based on the Shockley–Read–Hall (SRH) theory with WKB tunneling approximation
In order to comply with the high performance wide dynamic range CMOS image sensors (CIS) design methodology [6], the n-type Buried Channel (BC) MOSFETs were fabricated with 15 nm thick gate oxide rated at 5 V and used as in-pixel source follower
Summary
CMOS technology scaling enables high density IC integration and fast transistor operation. The fabrication of BC MOSFETs in a CIS compatible process was reported in [6], and the noise characterization was performed on a single BC MOSFET with small channel. In experimental validation, the Power Spectrum Density (PSD) results were shown only at 1k Hz without analysis on different biasing conditions, and the traps were assumed uniformly distributed in space and energy level. To the best of our knowledge, this is the first time that 1/f γ noise has been analyzed and modeled for BC MOSFETs at various gate biasing conditions This model is experimentally validated with BC MOSFETs fabricated in a 5V CIS compatible process.
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