Immersion Lithography Research Articles

Pixelated source and mask optimization for immersion lithography

Immersion lithography systems with hyper-numerical aperture (hyper-NA) (NA>1) have become indispensable in nanolithography for technology nodes of 45nm and beyond. Source and mask optimization (SMO) has emerged as a key technique used to further improve the imaging performance of immersion lithography. Recently, a set of pixelated gradient-based SMO approaches were proposed under the scalar imaging models, which are inaccurate for hyper-NA settings. This paper focuses on developing pixelated gradient-based SMO algorithms based on a vector imaging model that is accurate for current immersion lithography. To achieve this goal, an integrative and analytic vector imaging model is first used to formulate the simultaneous SMO (SISMO) and sequential SMO (SESMO) frameworks. A gradient-based algorithm is then exploited to jointly optimize the source and mask. Subsequently, this paper studies and compares the performance of individual source optimization (SO), individual mask optimization (MO), SISMO, and SESMO. Finally, a hybrid SMO (HSMO) approach is proposed to take full advantage of SO, SISMO, and MO, consequently achieving superior performance.

Novel Scanning Immersion Lithography for 3D Microfabrication

We propose the first time combining the merit of scanning and immersion lithography to fabricate 3D microstructure in this study. Via applying a matching liquid to reduce the diffraction error, the gap between the mask/resist becomes more tolerable. In addition, the liquid also act as a lubricant and a buffer for smooth movement of the mask/substrate. These advantages will benefit the performance of scanning lithography technique. The experimental results show that the large-area, 3D microstructure with excellent surface quality (Ravg<10 nm) can be successively fabricated based on this method. Besides, 3D microstructures with various geometries and functionalities can be generated by altering the shape of the mask pattern, or changing the scanning directions. The proposed SIL technique seems to be a promising way for fabricating 3D microstructure for optical applications.

The status and trend of novel process and technology in nano-IC manufacturing

The technology development of micro-nano electronics in global IC industry is summarized and reviewed in the present paper. There are many challenges and opportunities as the innovative devices and materials have gradually been applied to IC manufacture. As ITRS 2011 Roadmap shows that gate length will shrink to 20 nm in 2013, the industry mainstream manufacturing technologies of the nano-electronics seems moving toward the goal. It is well known that the IC technology development basically depends on material science. In Section 2, some new material and process technologies are highlighted, such as strained silicon, high K and metal gate, ultra-low K, 450 mm silicon wafer, and immersion lithography technologies are the foundation of IC manufacture. The process integration for advanced CMOS manufacture technology is discussed in Section 3. As an example, 20 nm process flow scheme is explained and some comparison is made to the precious generation technology. The main process flow difference between 28 nm technology and 20 nm technology is illustrated and some explanations are presented. In Section 4, 3D system packaging technology is introduced. Some preliminary TSV experimental data made by SMIC are shown. It is expected that 3D TSV Wide I/O would eventually be inevitable in 28 nm production and beyond. In Section 5, the research and development of nonvolatile memory are summarized, such as RRAM, PcRAM and MRAM. Some lab experimental and measurement results from SMIC are demonstrated. It is believed that PcRAM, which is relatively mature technology, mass production will probably come up in the mainland in a few years. In Section 6, a couple of new transistor architectures are introduced and some experimental data are demonstrated, such as local SOI and GAA, and some experimental data are shown. Finally, the comments for domestic R&D strategy in IC area are proposed to future IC R&D direction.

Direct nanopatterning of 100 nm metal oxide periodic structures by Deep-UV immersion lithography

Deep-UV lithography using high-efficiency phase mask has been developed to print 100 nm period grating on sol-gel based thin layer. High efficiency phase mask has been designed to produce a high-contrast interferogram (periodic fringes) under water immersion conditions for 244 nm laser. The demonstration has been applied to a new developed immersion-compatible sol-gel layer. A sol-gel photoresist prepared from zirconium alkoxides caped with methacrylic acids was developed to achieve 50 nm resolution in a single step exposure. The nanostructures can be thermally annealed into ZrO(2). Such route considerably simplifies the process for elaborating nanopatterned surfaces of transition metal oxides, and opens new routes for integrating materials of interest for applications in the field of photocatalysis, photovoltaic, optics, photonics or microelectronics.

Effect of Injection Parameters on Immersion Liquid during Wafer Scanning

Double patterning improves the development of immersion lithography, but it brings new challenges including the higher scanning velocity of wafer. In this paper, considering two typical injection types, the three-dimensional computational fluid dynamics model is developed to investigate the effect of injection parameters on immersion liquid during wafer scanning. By analyzing the velocity distribution of immersion flow and normal stress on the lens, the proper parameters of injection are proposed under the typical conditions, and the appropriate parameters which lead to effective renovation with low lens distortion are also given.

Talbot effect immersion lithography by self-imaging of very fine grating patterns

Talbot effect immersion lithography was investigated to improve resolution based on simulation results. The resolution limit of typical projection optics is determined by the wavelength λ of the light source and the numerical aperture. Alternatively, the Talbot effect forms self-images with no projection optics. For our simulations, the authors proposed using a mask with a Cr pattern illuminated by 193 nm ArF laser. The authors also assumed that the gap under the mask was filled with high-index immersion fluid of n = 1.64. The finite difference time domain (FDTD) optical simulation is shown for various pitches from 110 to 200 nm. So far, the distance of the self-imaging period has been estimated by second-order approximation, but the estimated result is found to differ significantly from the FDTD result. The periodic distance from low-order diffractive rays should be estimated by a higher-order approximation or an analytical method. Using Talbot effect immersion lithography, the one-dimensional line-and-space pattern of 60 nm pitch and the two-dimensional contact hole of 70 nm pitch can be transferred by a 193 nm light source.

56 nm pitch Cu dual-damascene interconnects with self-aligned via using negative-tone development Lithography-Etch-Lithography-Etch patterning scheme

In the attempts to push the resolution limits of 193nm immersion lithography, this work demonstrates the building of 3 metal level 56nm pitch copper dual-damascene interconnects, using Negative-Tone Development Lithography-Etch-Lithography-Etch (LELE) Patterning at line level. Line Resistance and intra-level capacitance can be affected by the double patterning integration, but a good process window has been demonstrated, showing no impact on RC performance. The introduction of a self-aligned via (SAV) process with a TiN hard-mask is able to provide a robust process window in terms of via-metal short yield at line and via level. SAV implementation at these dimensions also affects the aspect-ratio of the structures and leads to new challenges in metallization: optimized profile, without bowing or undercut, is mandatory to enable the filling of 28nm lines. The metal hard-mask has to be removed or at least faceted by erosion. This can be achieved by conventional RIE process optimization, but pushes the RIE selectivity to challenging limits. Physical dimensions on target and via chain yield have been demonstrated by fine tuning RIE process. Profile improvement can also be achieved by the introduction of new WET process, helping the removal of the metal hard-mask while being neutral to the ULK. We have demonstrated good yield and reliability with an integration using hard-mask wet removal.

ITRS lithography roadmap: status and challenges

Abstract Recent ITRS lithography roadmaps show a big technology decision approaching the semiconductor industry about how to do leading edge lithography. The need is rapidly approaching for the industry to select an option for the 22-nm half pitch, but no decision has been made yet. The main options for the 22-nm half pitch are extreme ultraviolet (EUV), ArF immersion lithography with multiple patterning, and maskless lithography. For the 16-nm half pitch, directed self-assembly (DSA) is also an option. The EUV has the most industry investment and is the closest to current lithography in the way it works but still faces challenges in tool productivity and defect-free masks. The nanoimprint needs to overcome the defect, contamination, and overlay challenges before it can be applied to the semiconductor production. Maskless lithography may be used first for prototyping and small volume products where mask costs per chip produced would be very high. Double patterning could be extended to multiple pattering, but would give tremendous process complexity and exponentially rising mask costs due to the many exposures needed per level. The DSA, which only recently has emerged from the research stage, has the potential for very high resolution but represents a huge change in how critical dimensions are formed and controlled.

Analysis of process characteristics of self-aligned multiple patterning

Graphical abstractDisplay Omitted Highlights? Self-aligned multiple patterning (SAMP) techniques for scaling to 5nm are studied. ? It is shown that extra masks are required to solve the overlay challenges. ? SATP is most cost-effective as it allows fewer masks with 2-D design flexibility. ? SASP process will most likely reach the maximum cycles of frequency multiplication. ? It is unlikely to adopt SAOP or EUV+SADP process in VLSI manufacturing. Spacer based self-aligned multiple patterning (SAMP), when combined with 193nm immersion or EUV lithography, can potentially drive the resolution of IC features down to 5-nm half pitch. By designing various mandrel patterns which further define the route of the following spacers, some SAMP techniques are more capable of driving up the feature density, while some others are favorable to reduction of process complexity by using fewer masks and allowing 2-D design flexibility. In this paper, we shall present a general analysis of several key issues of SAMP techniques: resolution capability, process complexity, overlay requirement, and performance.

Mask roughness impact on extreme UV and 193nm immersion lithography

The contribution of mask absorber line edge roughness on printed resist lines is studied for extreme UV and 193nm immersion lithography. Programmed roughness modules were designed for roughness transfer function evaluation on 88nm pitch line space patterns. The tested modules were designed applying variations of roughness amplitude and spatial frequency. Power spectral density analysis was performed on top-down SEM images. The effect of frequency roughness filtering by the lithographic optical system was studied with different illumination settings. It was found that, except for the degradation of the aerial image due to the filtering effect, less performing illuminations show an increased deterioration of the aerial image quality and thus contribute further to line edge roughness. A comparison with previous work was completed on different mask architectures and photoresist platforms. Resist performance can attenuate the roughness transfer from mask but at the cost of worse chemical gradient at the edges of the exposed regions.

Mask optimization approaches in optical lithography based on a vector imaging model

Recently, a set of gradient-based optical proximity correction (OPC) and phase-shifting mask (PSM) optimization methods has been developed to solve for the inverse lithography problem under scalar imaging models, which are only accurate for numerical apertures (NAs) of less than approximately 0.4. However, as lithography technology enters the 45 nm realm, immersion lithography systems with hyper-NA (NA>1) are now extensively used in the semiconductor industry. For the hyper-NA lithography systems, the vector nature of the electromagnetic field must be taken into account, leading to the vector imaging models. Thus, the OPC and PSM optimization approaches developed under the scalar imaging models are inadequate to enhance the resolution in immersion lithography systems. This paper focuses on developing pixelated gradient-based OPC and PSM optimization algorithms under a vector imaging model. We first formulate the mask optimization framework, in which the imaging process of the optical lithography system is represented by an integrative and analytic vector imaging model. A gradient-based algorithm is then used to optimize the mask iteratively. Subsequently, a generalized wavelet penalty is proposed to keep a balance between the mask complexity and convergence errors. Finally, a set of methods is exploited to speed up the proposed algorithms.

Environmentally Benign In-Line Cleaning Solutions for Immersion Lithography Tools

A pH neutral formulation 3x to perform the in-line cleaning of resists/topcoats contaminated immersion assembly efficiently and effectively has been developed. It is environmentally benign with no halides, no individual component having a flash point above 38°C or known to cause cancer, birth defects or other reproductive harm.

Escaping death: single-patterning contact printing for <inline-formula><math display="inline" overflow="scroll"><mrow><mn mathvariant="bold">32</mn><mo mathvariant="bold">/</mo><mn mathvariant="bold">28</mn></mrow></math></inline-formula>-nm logic technology nodes

As 193-nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28-nm technology nodes has been greatly facilitated by the just-in-time introduction of new process enablers that allow the support of flexible foundry-oriented ground rules alongside high-performance technology, without inhibiting migration to a single-pass patterning process. The incorporation of device-based performance metrics, along with rigorous patterning and structural variability studies, was critical in the evaluation of material innovation for improved resolution and CD shrink. Additionally, novel design changes for single patterning incorporating mask optimization efforts, along with new capability in data preparation, were assessed to allow for minimal impact of implementation of a single patterning contact process late in the 32-nm and 28-nm development cycles. In summary, this paper provides a comprehensive study of what it takes to turn a contact-level double-patterning process into a single-patterning process consisting of design and data manipulation, as well as wafer manufacturing aspects, together with many results.

SRAF Optimization for sub-40nm Technology Node Contact Patterning

As 193nm immersion lithography is extended to sub-40nm technology node, how to define a single-pass contact hole patterning process with enough common lithography process window is a very challenging task. Sub-resolution assist features (SRAF) optimization is one crucial step besides illumination optimization and mask bias optimization. This paper presents a comprehensive SRAF optimization flow that achieves a set of SRAF solutions that balances SRAF benefits and mask manufacturing feasibility. As the criterion of patterning performance, the through pitch process window is investigated for different SRAF placement options based on simulated PV-band of a given process variation (focus & dose). Full chip optimization with representative layouts is also studied. Silicon level performance verification is done with final SRAF solution for through pitch pattern and typical layouts. Finally, we conclude the paper by demonstrating the overall benefit of SRAF on CD uniformity, from process capability as well as mask complexity perspectives.

DOF and Coherence Optimization in Sub-32 nm Contact Lithography

As lithography process steps into deep low k1 factor (~0.3 or smaller) generation, imaging quality and lithography process window (PW) are highly sensitive to the illumination pupil. Maintaining the depth of focus (DOF) becomes more challenging for sub-32 nm tech node micro-lithographic process especially for contact patterns, and carefully selection of accurate illumination setting is significant during the course of process development. Although Source Mask Optimization (SMO) has become one of the most important techniques available for extending ArF immersion lithography, for logic and foundry patterns, source optimization only is still an effective method to extend lithographic capability and maximize depth of focus. In this paper, we present our study on the determination of the optimized illumination mode for 28 nm contact lithography through both photolithographic simulation and experiments with different imaging coherence settings. This simulation and experimental study show that even a previously believed "tiny" sigma change, such as, 0.01 can lead to a significant effect on depth of focus, which can be as much as 30%. This indicates that photolithographic process optimization and development have entered an era where intensive simulation and parameter mapping becomes inevitable in order to achieve success. Also, the heavy dependence of an acceptable process on the illumination has put a more stringent requirement on the scanner's control on the illumination pupil's accuracy and stability.

Cost of Ownership/Yield Enhancement of High Volume Immersion Lithography Using Topcoat-Less Resists

The complexity and extra cost associated with a resist topcoat layer has motivated the industry to transition to topcoat-less (TC-less) resist processes. By switching to TC-less resists, track suppliers are able to achieve higher throughput using less costly equipment, scanner suppliers can increase the scanning speed of their litho systems with minimized risk of defects, and end users eliminate a process step and gain increased output at a lower cost. These factors become increasingly critical as a result of the heightened processing complexities associated with double patterning lithography. In addition to reduction in process complexity benefits, a topcoat-less process must also satisfy the other critical performance criteria, and results for overlay, autofocus, and imaging will be discussed. To justify transition to a new process, there also should be demonstration of associated cost reduction or productivity improvements.

The status and trend of novel process and technology in nano-IC manufacturing

The technology development of micro-nano electronics in global IC industry is summarized and reviewed in the present paper. There are many challenges and opportunities as the innovative devices and materials have gradually been applied to IC manufacture. As ITRS 2011 Roadmap shows that gate length will shrink to 20 nm in 2013, the industry mainstream manufacturing technologies of the nano-electronics seems moving toward the goal. It is well known that the IC technology development basically depends on material science. In Section 2, some new material and process technologies are highlighted, such as strained silicon, high K and metal gate, ultra-low K, 450 mm silicon wafer, and immersion lithography technologies are the foundation of IC manufacture. The process integration for advanced CMOS manufacture technology is discussed in Section 3. As an example, 20 nm process flow scheme is explained and some comparison is made to the precious generation technology. The main process flow difference between 28 nm technology and 20 nm technology is illustrated and some explanations are presented. In Section 4, 3D system packaging technology is introduced. Some preliminary TSV experimental data made by SMIC are shown. It is expected that 3D TSV Wide I/O would eventually be inevitable in 28 nm production and beyond. In Section 5, the research and development of nonvolatile memory are summarized, such as RRAM, PcRAM and MRAM. Some lab experimental and measurement results from SMIC are demonstrated. It is believed that PcRAM, which is relatively mature technology, mass production will probably come up in the mainland in a few years. In Section 6, a couple of new transistor architectures are introduced and some experimental data are demonstrated, such as local SOI and GAA, and some experimental data are shown. Finally, the comments for domestic R&D strategy in IC area are proposed to future IC R&D direction.

Comparison of EUV Patterning between PTD and NTD for 2Xnm DRAM

The patterning performance of 3Xnm half pitch contact hole for 2Xnm DRAM was achieved from NXE3100, EUV pre-production tool last year. The local CD uniformity of EUV was comparable to that of immersion DPT (Double Patterning Technology), so the EUV patterning performance of 3Xnm half pitch is ready for mass production. But productivity progress of EUV source power is behind the plan and EUV shot noise is still problematic, so EUV resist process need to be improved for sub 3Xnm half pitch contact hole patterning. And also the patterning of sub 20nm half pitch line and space was gathered from NXE3100 but LWR and collapse are critical issues to be improved. Recently we introduced negative tone development (NTD) in immersion lithography for mass production and achieved excellent patterning performance compared to positive tone development (PTD) because negative tone development (NTD) showed better optical contrast on contact hole patterning and swelling-free property of resist film against developer. In this paper, we describe necessity of negative tone development (NTD) on EUV, optimization of mask cell size, upgrade status of resist and resolution limit between positive (PTD) and negative tone development (NTD).

Materials Development to Extend ArF Lithography Toward Sub-20nm Patterning

New Materials for 193nm lithography extension are widely in need, especially for post 193nm immersion lithography technology. In this paper, we would report the performance of shrink material for trench patterns on litho-etch-litho-etch double patterning process. This material contains directed self-assemble properties and it succeeded in forming 23nm trench patterns. Besides, we would also report a sliming material which is able to make line patterns smaller and it succeeded in forming 19nm line patterns. Both new materials are promising in improving original photoresist pattern quality for enhancing double patterning processes.

Patterning of 25 nm Contact Holes at 90 nm Pitch: Combination of Line/Space Double Exposure Immersion Lithography and Plasma-Assisted Shrink Technology

Patterning of 25 nm Contact Holes at 90 nm Pitch: Combination of Line/Space Double Exposure Immersion Lithography and Plasma-Assisted Shrink Technology