Immersion Lithography Research Articles

Advanced plasma etch technologies for nanopatterning

Advances in patterning techniques have enabled the extension of immersion lithography from 65/45 nm through 14/10 nm device technologies. A key to this increase in patterning capability has been innovation in the subsequent dry plasma etch processing steps. Multiple exposure techniques, such as litho-etch-litho-etch, sidewall image transfer, line/cut mask, and self-aligned structures, have been implemented to solution required device scaling. Advances in dry plasma etch process control across wafer uniformity and etch selectivity to both masking materials have enabled adoption of vertical devices and thin film scaling for increased device performance at a given pitch. Plasma etch processes, such as trilayer etches, aggressive critical dimension shrink techniques, and the extension of resist trim processes, have increased the attainable device dimensions at a given imaging capability. Precise control of the plasma etch parameters affecting across-design variation, defectivity, profile stability within wafer, within lot, and across tools has been successfully implemented to provide manufacturable patterning technology solutions. IBM has addressed these patterning challenges through an integrated total patterning solutions team to provide seamless and synergistic patterning processes to device and integration internal customers. We will discuss these challenges and the innovative plasma etch solutions pioneered by IBM and our alliance partners.

Compact PIN-Diode-Based Silicon Modulator Using Side-Wall-Grating Waveguide

We developed PIN-diode-based silicon Mach-Zehnder modulators, which have side-wall-gratings in the phase-shifter sections. Such passive waveguides with gratings were fabricated using ArF immersion lithography, which showed a small scattering loss of 0.4 dB/mm. We extensively investigated the forward-biased operation of the modulators by using equivalent circuit analysis and the measurement of the fabricated devices. We argue carrier recombination time only plays a minor role for the overall performance of the modulator. Dependences of the modulation efficiency on other various critical parameters are discussed. In particular, if we use relatively short phase shifter, the forward-biased operation provides smaller VπL than reversed one even at high frequency of 20 GHz, at the expense of the narrow bandwidth. Our approach enables high-speed operation up to 50 Gb/s, by using phase shifter as short as 250 μm and preemphasis signals. For 12.5-Gb/s operation, the modulator cell size was only 300 μm × 50 μm, which was suitable for the applications of high-density optical interconnects.

Si wire array waveguide grating with stray light reduction scheme fabricated by ArF excimer immersion lithography

A Si wire arrayed waveguide grating designed to reduce the noise and transmission peak width and avoid systematic phase error generated at the curved waveguides is reported. A slab waveguide structure to remove stray light is used. 200 GHz spacing 16 channel devices were fabricated by ArF immersion. An improved crosstalk of −23 dB was obtained.

Behaviors of Immersion Flow in Micro-Gap with Moving Boundary

In order to improve the flow stability when wafer scans at high speed, immersion lithography with small flow-thickness is proposed for the high resolution lithography. By using the three-dimensionally numerical methods, the immersion flow in micro-gap is investigated to analyze the behaviors of liquid flow. Based on the flow characteristics of typical structures with different liquid thickness and scanning speed, the liquid mean-velocity on account of thousand sample points in the exposure area are studied, and the appropriate parameters and method of effective renovation with small thickness are also given.

Lumped-Parameter Modeling of an Immersion Flow Field for Analyzing Meniscus Dynamic Behavior

Motivated by the interest to increase production throughputs of immersion lithography machines, wafers are scanned at increasingly high velocities and accelerations, which may result in liquid loss at the receding contact line. The dynamic characteristics of the immersion fluid with free boundary play an important role for fluid management system, and are concerned in various potential immersion unit designs. To offer intuitive insights into the dynamic effects of the immersion fluid due to scan speeds, a lumped-parameter model based on two-dimensional (2D) image data has been developed to characterize the 3D hydrodynamics of the immersion flow process. To validate the model, meniscus behavior information under dynamic conditions is extracted experimentally and analyzed using image processing techniques. The reduced model agrees qualitatively well with the experimental data.

Defect source analysis of directed self-assembly process

As design rule shrinks, it is essential that the capability to detect smaller and smaller defects should improve. There is considerable effort going on in the industry to enhance immersion lithography using directed self-assembly (DSA) for the 14-nm design node and below. While the process feasibility is demonstrated with DSA, material issues as well as process control requirements are not fully characterized. The chemical epitaxy process is currently the most-preferred process option for frequency multiplication, and it involves new materials at extremely small thicknesses. The image contrast of the lamellar line/space pattern at such small layer thicknesses is a new challenge for optical inspection tools. The study focuses on capability of optical inspection systems to capture DSA unique defects such as dislocations and disclination clusters over the system and wafer noise. The study is also extended to investigate wafer-level data at multiple process steps and to determine the contribution from each process step and materials using defect source analysis methodology. The added defect pareto and spatial distributions of added defects at each process step are discussed.

Improving Equipment Defectivity Specifications Through Chip Yield Modeling: A Case Study for Immersion Lithography

Semiconductor equipment suppliers are asked to build tools that can operate almost continuously. Once such a reliable tool is developed, defect data collection, understanding, and reduction become increasingly important since the tool has to manufacture reliable (layers of) semiconductor devices that scarcely fail. At this stage, semiconductor equipment suppliers could benefit from the concepts of chip yield modeling, because it directly relates their defect data to the yield of semiconductor devices. We present a case study in which we estimate the yield impact of defects related to immersion photolithography scanners. Defects were separated into various classes, and the size distributions of those classes were measured. Given a circuit's critical area, forecasting of the yield for any defect class becomes straightforward, and also yield predictions can be made for future technology nodes, resulting in the optimal choice of yield-enhancing strategies.

Hybrid source mask optimization for robust immersion lithography

To keep pace with the shrinkage of critical dimension, source and mask optimization (SMO) has emerged as a promising resolution enhancement technique to push the resolution of 193 nm argon fluoride immersion lithography systems. However, most current pixelated SMO approaches relied on scalar imaging models that are no longer accurate for immersion lithography systems with hyper-NA (NA>1). This paper develops a robust hybrid SMO (HSMO) algorithm based on a vector imaging model capable of effectively improving the robustness of immersion lithography systems to defocus and dose variations. The proposed HSMO algorithm includes two steps. First, the individual source optimization approach is carried out to rapidly reduce the cost function. Subsequently, the simultaneous SMO approach is applied to further improve the process robustness by exploiting the synergy in the joint optimization of source and mask patterns. The conjugate gradient method is used to update the source and mask pixels. In addition, a source regularization approach and source postprocessing are both used to improve the manufacturability of the optimized source patterns. Compared to the mask optimization method, the HSMO algorithm achieves larger process windows, i.e., extends the depth of focus and exposure latitude, thus more effectively improving the process robustness of 45 nm immersion lithography systems.

C- and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities

We report on integrated erbium-doped waveguide lasers designed for silicon photonic systems. The distributed Bragg reflector laser cavities consist of silicon nitride waveguide and grating features defined by wafer-scale immersion lithography and a top erbium-doped aluminum oxide layer deposited as the final step in the fabrication process. The resulting inverted ridge waveguide yields high optical intensity overlap with the active medium for both the 0.98 μm pump (89%) and 1.5 μm laser (87%) wavelengths with a pump-laser intensity overlap of >93%. We obtain output powers of up to 5 mW and show lasing at widely spaced wavelengths within both the C and L bands of the erbium gain spectrum (1536, 1561, and 1596 nm).

Block-based mask optimization for optical lithography

Pixel-based optical proximity correction (PBOPC) methods have been developed as a leading-edge resolution enhancement technique (RET) for integrated circuit fabrication. PBOPC independently modulates each pixel on the reticle, which tremendously increases the mask's complexity and, at the same time, deteriorates its manufacturability. Most current PBOPC algorithms recur to regularization methods or a mask manufacturing rule check (MRC) to improve the mask manufacturability. Typically, these approaches either fail to satisfy manufacturing constraints on the practical product line, or lead to suboptimal mask patterns that may degrade the lithographic performance. This paper develops a block-based optical proximity correction (BBOPC) algorithm to pursue the optimal masks with manufacturability compliance, where the mask is shaped by a set of overlapped basis blocks rather than pixels. BBOPC optimization is formulated based on a vector imaging model, which is adequate for both dry lithography with lower numerical aperture (NA), and immersion lithography with hyper-NA. The BBOPC algorithm successively optimizes the main features (MF) and subresolution assist features (SRAF) based on a modified conjugate gradient method. It is effective at smoothing any unmanufacturable jogs along edges. A weight matrix is introduced in the cost function to preserve the edge fidelity of the printed images. Simulations show that the BBOPC algorithm can improve lithographic imaging performance while maintaining mask manufacturing constraints.

Leaching and drying marks on photoresist-coated substrates

In immersion lithography, the probability to leave water on a photoresist (PR) increases with the scan speed. After wet processes, in general, liquid droplets may remain on the substrates. The evaporation of these droplets coupled with the leaching of the PR produces defects. These drying defects may affect the resolution of the subsequent lithographic exposure. Beyond lithography, this interaction droplet–PR is of great interest in ink-jet printing technology. Indeed, contrast and resolution depend on the pattern left after the evaporation of sessile droplets. Here, we analyze the drying speed of a sessile water droplet on a PR substrate with the aim to characterize the resulting drying marks by the dynamics of their formation and by their typical “crater” topography. First, we focus our study on the drying dynamics of an evaporating sessile droplet and its drying patterns left on the PR; second, we show that the contact line motion is the key feature in the generation of surface defects with a strong interaction fluid/surface despite the hydrophobicity.

Sub-30nm via interconnects fabricated using directed self-assembly

In this study, sub-30nm via interconnects were fabricated and fully integrated on a 300mm wafer using directed self-assembly lithography (DSAL). They were tested electrically and initial test results are reported. DSAL was applied on the via layer, which is connecting between the lower metal layer and the upper metal layer. A trilayer resist process was utilized for preparing a guiding pattern of graphoepitaxy. Exposure dose of 193nm immersion lithography was centered so that via size in spin-on-carbon (SOC) was just 70nm in diameter. Poly (styrene-block-methyl methacrylate) (PS-b-PMMA) block copolymer (BCP) solution was applied on the SOC pre-pattern, and then annealed in N2 atmosphere to induce micro-phase separation. PMMA domain was finally transferred into a dTEOS oxide film as a via hole. Via interconnects were fabricated using tungsten deposition followed by CMP. Intra-wafer variation of via resistance was measured and the correlation between the via resistance and the via dimension was discussed.

(Keynote) Advanced Lithography for Density Scaling

Despite the widening gap between scaled feature sizes and optical exposure wavelengths, integrated circuit transistor density so far has kept pace with Moore’s Law. The absence of viable lens materials for smaller wavelengths precludes exposure wavelengths below 193nm for refractive optical tools. Reflective optical exposure tools using extreme ultraviolet (EUV) light have been under intense development over the past decade but, mainly due to light source power shortfalls, have not yet achieved performance levels needed for high volume production. Alternatives to optical pattern transfer are also under development, including electron beam direct write, and nano-imprint lithography (NIL) systems. Until EUV or an alternative technology meets high-volume production requirements, next-generation integrated circuit process nodes will rely upon 193nm immersion lithography tools augmented with novel optical and process technologies to achieve feature pitches below the single exposure resolution limit. Squeezing more information through the limited spatial bandwidth of 193nm systems imposes limitations on design layout freedoms. Designers can no longer draw arbitrary patterns even when minimum line and space dimension constraints are met. The types of layout restrictions demanded by alternative lithography approaches, and their impact on patterning resolution and noise trade-offs, are explored in the context of evolving IC end-use values, such as density, performance, and power efficiency.

Si wire array waveguide grating with parallel star coupler configuration fabricated by ArF excimer immersion lithography

An Si wire array waveguide grating wavelength demultiplexer fabricated using immersion ArF lithography is reported. The tilt directions of the input and output star couplers are aligned in the same direction to avoid phase error generated at the curved waveguides. A 16 channel device with 200 GHz wavelength spacing was fabricated.

Thermal behavior of wafers and its effects on overlay performance in immersion lithography

In semiconductor manufacturing below 45nm node, immersion lithography is serious technique to increase depth of focus (DOF) at obtainable apertures and to improve resolution with apertures higher than one. However, immersion environment between wafer and lens could be responsible for a net reduction in overlay performance due to wafer temperature instability during exposure. In this paper, we have investigated correlation of thermal behavior of wafer during exposure and overlay performance. It was founded that the thermal effect of concentric distribution on wafer scaling (correctable errors) is lager (0.1ppm) than uniform distribution. In grid and field residual analysis, the grid residual errors was demonstrated a good correlation (R^2=0.92) with thermal variation. However, there was little relationship (R^2=0.3) between the field residual errors and thermal stability. These results indicated that progressed thermal controllability for both spatial and temporal variation can be converted into improved overlay accuracy in immersion lithography.

Transfer of a continuous-relief lenticular array onto a quartz substrate by using SIL combined with the dry-etching method

This study presents the technological process for producing a lenticular array on quartz. With scanning immersion lithography used to define the 3D lenticular array structure on a quartz substrate, inductively coupled plasma-reactive ion etching (ICP-RIE) is able to directly etch the structure. Based on the surface measurement, ICP-RIE can completely etch the surface structure onto the quartz substrate, and the surface roughness can reach 30 nm. Furthermore, after the optical measurement of stereoscopic images, the left and the right stereoscopic images can be successfully transmitted to the corresponding places without crosstalk and with a splitting efficiency close to 80%. As a result, this technology allows for the production of a lenticular structure with various changes on the quartz surface.

Material Development for ArF Immersion Extension towards Sub-20nm Node

Today ArF immersion processes are widely applied for advanced device manufacturing. ArF immersion lithography enables 4x nm half-pitch (hp) lithography. The use of double patterning extends immersion to 2x nm hp lithography. New materials for such 193nm lithography extensions are widely needed, especially for post-193nm immersion lithography technology. In this paper, we report a slimming material that makes line patterns smaller and it succeeds in forming 20nm lines.In another study, we examined a new hydrophilic lactone to improve line width roughness (LWR) and defectivity. First, we studied the lactone reactivity with developer and its behavior during development. Then we verified its line width LWR performance and defectivity. When the hydrophilic new lactone is used in a photoresist, an improvement in LWR and defectivity photoresist was observed. This is very useful progress, especially in combination with processes such as multiple patterning to extend ArF immersion to sub-20nm hp dimensions.

Analysis and optimization approaches for wide-viewing-angle λ/4 plate in polarimetry for immersion lithography

A waveplate is usually used to measure the polarization effects in optical systems. For a hyper numerical aperture imaging system with a large angle of incidence, the incident plane of light concerned may be neither parallel nor perpendicular to the optical axis of the waveplate, which makes a conventional waveplate produce undesired nonuniform retardation in any incident plane determined by the incident light and the wave normal of the crystal surface. To compensate effectively for this nonuniform retardation, the authors propose approaches to analyze and optimize the wide-viewing-angle (WVA) λ/4 plate. First, the retardation between the p and s components of a light wave propagating through the WVA waveplate is analyzed based on light propagation theory. Then, the authors develop an optimization method for the thickness parameters of the waveplates that compose the WVA λ/4 plate, which is used extensively in polarimetry for immersion lithography. It is found that the proposed approach is effective for W...

Flow Characteristics for High-Speed Scanning in Immersion Lithography

High-speed scanning is an effective way to improve the throughput of immersion lithography with double patterning, especially when the critical dimension is less than 32-nm. But it makes more complex characteristics of immersion flow. In this paper, considering the extreme speed of wafer scanning, the model is developed to investigate the characteristics of immersion flow, including the velocity vector, pressure distribution, renovation efficiency and so on. Finally, the optimized parameters and methods to effective liquid renovation are proposed when the wafer scans at high-speed.

Maximal Air Bubble Entrainment at Liquid-Drop Impact

At impact of a liquid drop on a solid surface, an air bubble can be entrapped. Here, we show that two competing effects minimize the (relative) size of this entrained air bubble: for large drop impact velocity and large droplets, the inertia of the liquid flattens the entrained bubble, whereas for small impact velocity and small droplets, capillary forces minimize the entrained bubble. However, we demonstrate experimentally, theoretically, and numerically that in between there is an optimum, leading to maximal air bubble entrapment. For a 1.8mm diameter ethanol droplet, this optimum is achieved at an impact velocity of 0.25 m/s. Our results have a strong bearing on various applications in printing technology, microelectronics, immersion lithography, diagnostics, or agriculture.