IGZO Thin-film Transistors Research Articles

Comparative Study of Atomic Layer Deposition Supercycle Design Effects on Reliability in Heterogeneous IGZO Channel TFTs

Oxide semiconductor thin-film transistors (TFTs) are promising candidates for application in display backplanes and memory devices. To ensure both high performance and stable electrical properties of oxide TFTs over long-term use, superior mobility and device stability need to be obtained. In this regard, atomic layer deposition (ALD) has gained attention as a facile method for obtaining conformal oxide films under defect-free conditions and adjusting the composition or distribution for targeted TFT performance. Here, we propose that, even with the same bulk composition, variations in the local composition using an ALD supercycle design can significantly affect the TFT performance, particularly the bias-temperature stability. To ascertain the influence of the local cation distribution on the performance, we compared two supercycle designs by reversing the sub-cycles of indium, gallium, and zinc with identical bulk In–Ga–Zn ratios. Despite minimal changes in the electrical characteristics, such as the mobility and threshold voltage, of the two TFTs designed with ALD supercycles, there was a significant difference in their reliability. Devices with an indium-rich IGZO active layer on the back channel exhibited a hump phenomenon and approximately five times greater Vth degradation (ΔVth: -0.67 V to -3.36 V). By conducting an additional case study of IGZO TFTs and film analysis, we confirmed that mobility is largely governed by the bulk composition, whereas the local surface composition, serving as the back channel, is the key to reliability. The device performance results could be confirmed through the surface and bulk analyses of heterogeneous films engineered through the ALD supercycle design. Furthermore, it has been proposed that optimizing the ALD supercycle design is the key to obtaining high-performance oxide semiconductor TFTs.

Low-Voltage IGZO Field-Effect Ultraviolet Photodiode

Abstract In the era of Internet of Things (IoTs), an energy-efficient ultraviolet (UV) photodetector (PD) is highly desirable considering the massive usage scenarios such as environmental sterilization, fire alarm and corona discharge monitoring. So far, common self-powered UV PDs are mainly based on metal-semiconductor hetero-structures or p–n heterojunctions, where the limited intrinsic built-in electric field restricts further enhancement of the photoresponsivity. In this work, an extremely low-voltage field-effect UV PD is proposed using a gate-drain shorted amorphous IGZO (a-IGZO) thin film transistor (TFT) architecture. A combined investigation of the experimental measurements and technology computer-aided design (TCAD) simulations suggests that the reverse current (I R) of field-effect diode (FED) is highly related with the threshold voltage (V th) of the parental TFT, implying an enhancement-mode TFT is preferable to fabricate the field-effect UV PD with low dark current. Driven by a low bias of −0.1 V, decent UV response has been realized including large UV/visible (R 300/R 550) rejection ratio (1.9 × 103), low dark current (1.15 × 10−12 A) as well as high photo-to-dark current ratio (PDCR, ∼ 103) and responsivity (1.89 A/W). This field-effect photodiode provides a new platform to construct UV PDs with well-balanced photoresponse performance at a low bias, which is attractive for designs of large-scale smart sensor networks with high energy efficiency.

P‐12: Improve the Reliability of a‐IGZO TFT through Optimizing the Threshold Voltage and Channel Thickness in AMOLED Hybrid Backplane

In the fabrication of flexible a‐IGZO and LTPS thin film transistor (TFT) hybrid backplane, various threshold voltage (Vth) of the a‐IGZO TFT was achieved in this paper by regulating the O2/Ar ratio during the deposition of a‐IGZO film by sputtering. The results show that the Vth increases with the increase of the O2/Ar ratio, and the reliability tests indicate that in a certain range negative adjustment of Vth can significantly improve the positive bias temperature instability (PBTI) of IGZO TFT, and maintain good electrical uniformity. The increase of the O2/Ar ratio reduces the number of oxygen vacancy (Vo) in the a‐IGZO channel, and thereby Vth is positively shifted, which is confirmed by the TCAD simulation. The Vth value can indicate the Vo concentration in a‐IGZO TFT channel partly, and appropriately higher amount of Vo is beneficial to improve the PBTI, which is attributed to Fermi level (EF) shifting closer to conduction band. Raised EF means less unoccupied trap states, resulting in less carrier trapping under PBTI. Furthermore, the research also explores different a‐IGZO channel thicknesses and finds that when the Vth values are similar, thinner channel layers endow a‐IGZO TFT with improved PBTI. By optimizing the Vth and channel thickness, a‐IGZO TFTs with a channel thickness of 25nm and a Vth value of 0.2V have been prepared in a hybrid backplane. Under positive bias temperature stress for 5 hours, the Vth is positively shifted less than 0.5 V, which could lay the foundation for achieving high‐reliability flexible backplane for AMOLEDs.

30‐2: Hydrogen Contents Controlled Silicon Nitride Passivation Layer for Highly Reliable IGZO Thin Film Transistor

To achieve a highly reliable IGZO transistor, silicon nitride thin film, as a passivation layer, has been extensively investigated in recent years, mainly due to readily available fabrication, along with good barrier performance. Here, we found out that larger amount hydrogen residuals was observed in the PECVD deposited SiNx passivation layer, more stable the IGZO oxide device exhibited, which is abnormal behavior to that commonly known in the literatures. Given that FT‐IR and SIMS analysis with various controlled SiNx thin film upon different deposition conditions, the plasma parameters such as power, pressure, source gas ratio could affect hydrogen ion diffusivity into the IGZO layer during the deposition and the chemical composition of hydrogen residuals in the resulting SiNx layer, which is more dominant, rather than absolute hydrogen contents itself, to the initial electrical properties as well the stability of the IGZO transistor device.

Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Defect annihilation of the IGZO/SiO2 layer is of great importance to enhancing the bias stress stabilities of bottom-gate coplanar thin-film transistors (TFTs). The effects of annealing temperatures (Ta) on the structure of the IGZO/SiO2 layer and the stabilities of coplanar IGZO TFTs were investigated in this work. An atomic depth profile showed that the IGZO/SiO2 layer included an IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. Higher Ta had only one effect on the IGZO layer and SiO2 layer (i.e., strengthening chemical bonds), while it had complex effects on the interfacial mixing layer—including weakening M-O bonds (M: metallic elements in IGZO), strengthening damaged Si-O bonds, and increasing O-related defects (e.g., H2O). At higher Ta, IGZO TFTs exhibited enhanced positive bias temperature stress (PBTS) stabilities but decreased negative bias temperature stress (NBTS) stabilities. The enhanced PBTS stabilities were correlated with decreased electron traps due to the stronger Si-O bonds near the interfacial layer. The decreased NBTS stabilities were related to increased electron de-trapping from donor-like defects (e.g., weak M-O bonds and H2O) in the interfacial layer. Our results suggest that although higher Ta annihilated the structural damage at the interface from ion bombardment, it introduced undesirable defects. Therefore, to comprehensively improve electrical stabilities, controlling defect generation (e.g., by using a mild sputtering condition of source/drain electrodes and oxides) was more important than enhancing defect annihilation (e.g., through increasing Ta).

Bias stress stabilities of PMMA-passivated indium-gallium-zinc-oxide thin-film transistors after 100 °C steam exposure

Bias stress stabilities of the polymethyl methacrylate (PMMA)-passivated IGZO thin-film transistors (TFTs) after being exposed in a normal and harsh (100 °C steam) environment were studied, in order to comprehensively evaluate protection effects of PMMA. In a normal environment, the PMMA-passivated TFTs exhibited normal switching characteristics and electrical stabilities. However, the switching characteristics and bias stress stabilities were changed after being exposed on 100 °C steam. There were negative Vth shifts on the transfer curves of the steam-exposed IGZO TFTs. Our XPS analysis revealed that the negative ΔVth was related to the steam-induced H2O molecules throughout the IGZO films, which acted as electron donors to introduce more electrons in the front channel. Under PBS, the steam-exposed IGZO TFTs showed an abnormal negative Vth shift while the un-exposed IGZO TFTs showed negligible Vth shift. This abnormality was ascribed to the electrons released from steam-induced H2O molecules, which render the conductive path more easily opened. Under NBS, the steam-exposed IGZO TFT presented larger negative Vth shift than the un-exposed TFT. This result was interpreted in terms of the steam-induced donor states (H2O molecules) near or at channel/insulator interface. Under PBTS and NBTS, the changes in Vth for steam-exposed TFTs were similar to those for un-exposed TFTs. Such a similarity indicates that steam exposure had no effects on NBTS and PBTS stabilities. It was understood in terms that the steam-induced H2O+ recombined with the electrons released from the steam-induced H2O molecules under bias stress, forming H2O to compensate the thermally-induced H2O adsorption. Our results suggest that one-micron-thick PMMA passivation layer enabled to protect IGZO TFTs from H2O in a normal environment, but it provided inadequate protection in a harsh environment. Therefore, a thicker PMMA passivation layer should be considered.

Tailoring Subthreshold Swing in A-IGZO Thin-Film Transistors for Amoled Displays: Impact of Conversion Mechanism on Peald Deposition Sequences.

Amorphous IGZO (a-IGZO) thin-film transistors (TFTs) are standard backplane electronics to power active-matrix organic light-emitting diode (AMOLED) televisions due to their high carrier mobility and negligible low leakage characteristics. Despite their advantages, limitations in color depth arise from a steep subthreshold swing (SS) (≤ 0.1 V/decade), necessitating costly external compensation for IGZO transistors. For mid-size mobile applications such as OLED tablets and notebooks, it is important to ensure controllable SS value (≥ 0.3 V/decade). In this study, a conversion mechanism during plasma-enhanced atomic layer deposition (PEALD) is proposed as a feasible route to control the SS. When a pulse of a diethylzinc (DEZn) precursor is exposed to the M2O3 (M = In or Ga) surface layer, partial conversion of the underlying M2O3 to ZnO is predicted on the basis of density function theory calculations. Notably, significant distinctions between In-Ga-Zn (Case I) and In-Zn-Ga (Case II) films are observed: Case II exhibits a lower growth rate and larger Ga/In ratio. Case II TFTs with a-IGZO (subcycle ratio of In:Ga:Zn = 3:1:1) show reasonable SS values (313mV decade-1) and high mobility (µFE) of 29.3cm2 Vs-1 (Case I: 84mV decade-1 and 33.4cm2 Vs-1). The rationale for Case II's reasonable SS values is discussed, attributing it to the plausible formation of In-Zn defects, supported by technology computer-aided design (TCAD) simulations.

Improvement of the electrical properties of amorphous indium-gallium-zinc oxide thin-film transistors by cross-linked CYTOP passivation

In this study, we investigated the effect of a cross-linked CYTOP passivation layer on the electrical properties of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). Cross-linked CYTOP passivation showed a deeper fluorine diffusion depth than CYTOP passivation owing to the chemical reaction between the cross-linking agent and IGZO layer. The cross-linking agent reduces the weakly bonded oxygen in the IGZO layer via a chemical reaction, enhancing fluorine diffusion into the IGZO layer. Therefore, the effect of fluorine on the IGZO layer was enhanced by using cross-linked CYTOP as a passivation layer. The diffused fluorine reduced the defect states by passivating the oxygen-related defects such as oxygen vacancies and weakly bonded oxygen and increased the carrier concentration by replacing metal–oxygen bonds with metal-fluorine bonds. IGZO TFTs with cross-linked CYTOP passivation exhibited a threshold voltage of −0.35 V, saturation mobility of 1.93 cm2/V∙s, and subthreshold swing of 0.53 V/dec. Using a cross-linked passivation layer also improved the reliability under positive gate bias stress. Consequently, a cross-linked CYTOP passivation layer can effectively improve the electrical properties of IGZO TFTs by incorporating fluorine atoms into the IGZO layer.

Improved mobility and bias stability of Hf-doped IGZO/IZO/Hf-doped IGZO thin-film transistor

Amorphous In–Ga–Zn–O (a-IGZO) thin-film transistor (TFTs) have attracted considerable attention owing to their advantages such as low leakage current and high optical transparency. However, because of their low mobility and bias instability, a-IGZO TFTs have limited applications in next-generation displays. Here, a TFT with Hf-doped a-IGZO (IGZO:Hf) and IZO multichannel layers is proposed to solve this problem. Hf easily combines with surrounding oxygen ions; thus, the IGZO:Hf layer improves the stability of TFT by reducing the oxygen vacancies and suppressing the oxygen-related defects. The IZO layer increases the number of free carriers in the channel layer owing to the formation of oxygen vacancies during the annealing process. Further, a two-dimensional electron gas is formed at the interface between the IGZO:Hf and IZO layers, accumulating free carriers near the interface. The optimized TFT with IGZO:Hf/IZO/IGZO:Hf channel layers exhibited a high field-effect mobility (≈40 cm2/V s), high on/off ratio (>107), and low subthreshold swing (≈222 mV/dec). Moreover, it showed excellent stability with a threshold voltage shift of less than 1 V, even under various bias stress conditions. This approach provides a crucial avenue to improve the overall performance of metal oxide-based TFTs.

Energy-Band Engineering By Remote Doping of Self-Assembled Monolayers Leads to High-Performance Igzo/P-Si Heterostructure Photodetectors

Advancements in emerging technologies, such as autonomous driving, artificial intelligence, medical imaging, and augmented reality, have increased the demand for high-resolution image sensors to transmit further accurate color information. To meet the performance requirements of these applications, several research have been accelerating towards the utilization of emerging low-dimensional semiconductor materials, such as metal oxides, transition metal dichalcogenides, perovskites, and other organic materials.Among them, metal oxide semiconductors (MOSs) are potential candidates for developing high-performance photodetectors. It can be synthesized over large areas using a simple/low-temperature process and are compatible with conventional fabrication equipment. However, MOS-based photodetectors still have several limitations, 1) the presence of charge traps and operational instability on the oxide surface, which degrade photodetection performance, and 2) the absence of an appropriate doping technique for MOS has blocked to improve photodetection performance via materials characteristic modification method.In this study, we present a strategy to overcome these limitations and significantly enhance the performance of IGZO, which is representative of oxide semiconductor thin film, based photodetector with high operation stability and sustainability under ambient atmospheres. We utilized energy-band engineering through an octadecylphosphonic acid (ODPA) self-assembled-monolayer (SAM)-based doping treatment to enhance the photoelectric characteristics of IGZO/p-Si hetero-interfaced devices (ISH). The ODPA consists of a head group of the hydroxyl group, which forms the self-assembled covalent bond formation of R–P–O–substrate. Combining the ODPA SAM with the oxide surface of IGZO provided carrier concentration control based on their a dipole effect, and remain the performance and functionality through the surface encapsulation. As a result, under a light-emitting diode (LED) wavelength with an intensity of 3.9 mW, the proposed device exhibited remarkable photo-switching current ratio of 4.33 × 103 A/A and negative differential resistance (NDR) phenomenon. Espacially, the dark current of the ODPA treated ISH is decreased about 10 times lower than as-fabricated ISH, which shows the possibility of signal noise minimization. These performance improvement is expected to be derived from band properties modulation through IGZO layer annealing and ODPA doping. To clarify the doping effect of each treatment, we characterized the ODPA self-assembled monolayer using X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), and Kelvin probe force microscopy (KPFM) to provide comprehensive analysis of the heterointerface effects. We also characterized the electrical properties of IGZO thin-film transistors (TFTs) based on variations of the annealing temperature to clarify the ODPA doping effect.We evaluated 156 ODPA-treated IGZO/p-Si heterostructure photodetectors, which were scaled for fabrication on a 4 inch wafer. The devices exhibited a 100% yield, and uniform current behavior in the dark state (0.20 ± 0.06 nA) and light state (0.87 ± 0.15 µA), owing to an evenly deposited IGZO layer and a simple-to-treat ODPA doping scheme. Furthermore, consecutive sweeps of 20,000 cycles verified excellent cycle-to-cycle endurance, resulting in highly robust photoelectric behaviors without operational failure. Additionally, the performance of the ODPA-treated, IGZO/p-Si heterostructure photodetector remained unchanged for 237 days without degradation under atmospheric exposure (relative humidity (RH) = 37–53 % and 20.6–23.1 °C). Acknowledgements This research was supported by funding supports from the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (NRF-2020R1A2C1101647) and Korea government (MEST) (NRF-2017R1A2B3011222). Figure 1

Enhancement in Performance and Reliability of Transparent IGZO Thin-Film Transistors by ITO/Ti Stacked Source/Drain Contacts

Enhancement in performance and reliability of transparent IGZO thin-film transistor (TFT) was achieved by adopting a laminated structure with a thin ITO layer and an ultrathin Ti layer as the source/drain (S/D) contacts. Compared with the transparent TFT with pure ITO S/D contacts, the transparent TFT with the ITO/Ti S/D contacts showed three times of enhancement in field-effect mobility from 4.75 to 12.10 cm2/Vs, two times of enhancement in on/off current ratio from 7.0 × 107 to 1.54 × 108, three times of reduction in contact resistance from 15.74 to 4.64 kΩ, and a decrease in threshold voltage from 3.11 V to 2.80 V. The TFT with the ITO/Ti S/D contacts also maintained an extremely low leakage current at zero gate bias (for the device with channel width/channel length of 40 μm/5 μm, the leakage current was ∼1 × 10−13 A). In addition, the TFT with the ITO/Ti S/D contacts showed a hump-free transfer curve and a smaller shift in threshold voltage under negative bias illumination stress. The enhancement in performance and reliability makes the transparent TFT with the ITO/Ti S/D contacts very promising in transparent display applications.

Total-Ionizing-Dose Effects in IGZO Thin-Film Transistors

Total-ionizing-dose (TID) effects are evaluated in back-gated IGZO thin-film transistors irradiated under different gate biases. Negative-bias irradiation leads to worst-case degradation of TID response in these devices, primarily as a result of enhanced charge trapping in the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> overlayer. The relatively small peak transconductance decrease after irradiation illustrates that IGZO transistors are much less sensitive to interface-trap buildup and other instabilities due to hydrogen release and transport than amorphous Si thin film transistors examined previously. The TID response of devices with different gate sizes is also investigated. No significant geometry dependence is observed, which is promising for future scaling down of the technology.

Realization of Visible‐Light Detection in InGaZnO Thin‐Film Transistor via Oxygen Vacancy Modulation through N2 Treatments

AbstractInGaZnO (IGZO) thin‐film transistors (TFTs) have gained widespread use in active matrix (AM) displays due to their decent field‐effect mobility and low off current. However, the wide bandgap of IGZO limits their application in visible light detection. This study presents an industry process‐compatible method to achieve visible light detection in IGZO TFTs through N2 treatment during the sputtering and annealing process for the first time. A comparison with control IGZO TFTs shows that the N2‐treated IGZO TFTs exhibit a high responsivity of 0.66 A W−1 and detectivity of 5.40 × 1014 Jones for visible light detection. Based on X‐ray photoelectron spectroscopy analysis and technology computer‐aided design simulations, a model, focusing on oxygen vacancy modulation, is proposed to explain the visible‐light sensitivity in IGZO TFTs with N2 treatment. This work opens up new possibilities for the integration of IGZO photodetector into AM display panels to realize in‐cell environmental detection and biometric recognition.

Thermally Activated Defect Engineering for Highly Stable and Uniform ALD-Amorphous IGZO TFTs with High-Temperature Compatibility.

Highly stable IGZO thin-film transistors derived from atomic layer deposition are crucial for the semiconductor industry. However, unavoidable defect generation during high-temperature annealing results in abnormal positive bias temperature stress (PBTS). Herein, we propose a defect engineering method by controlling the gate insulator (GI) deposition temperature. Applying a GI deposition temperature of 400 °C to the In0.52Ga0.18Zn0.30O active layer effectively suppresses defects even after 600 °C annealing, preserving the amorphous phase of IGZO. The device exhibits a threshold voltage (VTH) of 0.05 V, a field-effect mobility of 27.6 cm2/Vs, a subthreshold swing of 61 mV/decade, and a hysteresis voltage of 0.01 V, demonstrating highly reliable PBTS and negative bias temperature stress. A power-law fit of the PBTS stability under 2 MV/cm of gate field stress and 120 °C of temperature stress predicts a VTH shift of -0.01 V after 10 years. Moreover, the proposed method ensures reliable uniformity over a large 4 in. area.

Selectively Nitrogen Doped ALD-IGZO TFTs with Extremely High Mobility and Reliability.

Achieving high mobility and reliability in atomic layer deposition (ALD)-based IGZO thin-film transistors (TFTs) with an amorphous phase is vital for practical applications in relevant fields. Here, we suggest a method to effectively increase stability while maintaining high mobility by employing the selective application of nitrous oxide plasma reactant during plasma-enhanced ALD (PEALD) at 200 °C process temperature. The nitrogen-doping mechanism is highly dependent on the intrinsic carbon impurities or nature of each cation, as demonstrated by a combination of theoretical and experimental research. The Ga2O3 subgap states are especially dependent on plasma reactants. Based on these insights, we can obtain high-performance indium-rich PEALD-IGZO TFTs (threshold voltage: -0.47 V; field-effect mobility: 106.5 cm2/(V s); subthreshold swing: 113.5 mV/decade; hysteresis: 0.05 V). In addition, the device shows minimal threshold voltage shifts of +0.45 and -0.10 V under harsh positive/negative bias temperature stress environments (field stress: ±2 MV/cm; temperature stress: 95 °C) after 10000 s.

High-Speed Current Switching of Inverted-Staggered Bottom-Gate a-IGZO-Based Thin-Film Transistors with Highly Stable Logic Circuit Operations

High-speed electronic (HSE) systems are an emerging technology with potential applications in various fields, including biomedical imaging devices, display systems, ultrasound detectors, and object recognition. This report presents a study on low-temperature processed inverted-staggered bottom-gate a-IGZO thin-film transistors (TFTs) for measuring fast current switching at higher frequencies. The IGZO TFT exhibits an excellent mobility of 10.51 cm2/(V·s) and a higher on/off ratio of 3.2 × 105. Additionally, it displays highly stable and reliable gate-pulse switching at different frequencies ranging from 1 kHz to 0.2 MHz. Furthermore, logic operations such as inverter, NAND, and NOR gates were successfully performed using the enhancement-type device configuration. The results show stable and reliable voltage transfer responses with respect to the device configurations. Thus, this study not only enables the development of the applicability of the IGZO material in logic operations but also in HSE systems.

Mechanism of External Stress Instability in Plasma-Enhanced ALD-Derived HfO2/IGZO Thin-Film Transistors

In this article, the mechanism of stability in amorphous indium-gallium-zinc oxide ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{a}$</tex-math> </inline-formula> -IGZO) thin-film transistors (TFTs) with a natural length of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 8 nm was investigated from the perspective of hafnium oxide (HfO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}\text{)}$</tex-math> </inline-formula> gate dielectric point defects. The point defects in HfO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> responded to external stresses such as electric field ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{E}\text{)}$</tex-math> </inline-formula> and temperature. In particular, oxygen vacancies and the positively charged defects caused an abnormal negative shift in threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{TH}}\text{)}$</tex-math> </inline-formula> under positive gate bias temperature stress (PBTS). Therefore, reducing the positively charged defects was important to eliminate the abnormal behavior. Inserting a 0.7-nm-thick ultrathin SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> interlayer between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{a}$</tex-math> </inline-formula> -IGZO and optimized HfO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> further improved device performance including stability. Consequently, the resultant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{a}$</tex-math> </inline-formula> -IGZO TFT exhibited promising device performance with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu_{\text{FE}}$</tex-math> </inline-formula> of 22.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 0.5 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text{2}}$</tex-math> </inline-formula> V <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-\text{1}}$</tex-math> </inline-formula> s <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-\text{1}}$</tex-math> </inline-formula> , subthreshold swing (SS) of 64 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 0.5 mVdec <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-\text{1}}$</tex-math> </inline-formula> , hysteresis of 4 mV, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \textit{V}_{\text{TH}}$</tex-math> </inline-formula> of 124 mV under harsh PBTS with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{E}$</tex-math> </inline-formula> of 4 MV/cm at 80 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C for 3600 s.

Optimization of electrical performance and stability of fully solution-driven α-InGaZnO thin-film transistors by graphene quantum dots

• Fully solution-derived GQDs-IGZO TFTs based on ZrO 2 as gate dielectrics have been achieved. • GQDs-IGZO TFTs devices with optimized doping content have demonstrated improved performances, including a μ FE of 35.91 cm 2 V –1 s –1 , a higher I ON / I OFF of 5.04 × 10 8 , a smaller subthreshold swing (SS) of 0.11 V dec –1 and a smaller interfacial trap states of 1.57 × 10 12 cm −2 . • Resistor-loaded unipolar inverter based on GQDs-IGZO/ZrO x has been integrated, demonstrating good dynamic behavior and a high gain of 9.3. • LFN characteristics of GQDs-IGZO/ZrO x TFTs have suggested that the fluctuations in mobility are the noise source. This work presents solution-processed high-performance graphene quantum dots (GQDs) decorated amorphous InGaZnO (α-IGZO) thin-film transistors (TFTs) based on ZrO x as gate dielectrics. Compare with pure IGZO TFTs, GQDs-modified α-IGZO TFTs devices with optimized doping content have demonstrated better performances, including a larger field-effect mobility ( μ FE ) of 35.91 cm 2 V –1 s –1 , a higher on/off current ratio ( I ON / I OFF ) of 5.04 × 10 8 , a smaller subthreshold swing (SS) of 0.11 V dec –1 and a smaller interfacial trap states ( D it , 1.57 × 10 12 cm −2 ). Moreover, the GQDs-doped IGZO TFTs with a doping concentration of 0.5 mg ml –1 have shown excellent stability under bias stress and illumination stress conditions. To demonstrate the potential applications of α-IGZO TFTs in logic circuits, a resistor-loaded unipolar inverter based on GQDs-IGZO/ZrO x has been integrated, demonstrating good dynamic behavior and a high gain of 9.3. Low-frequency noise (LFN) characteristics of GQDs-IGZO/ZrO x TFTs have suggested that the fluctuations in mobility are the noise source. Based on all the experimental findings, it can be concluded that solution-processed GQDs-IGZO/ZrO x TFT may envision promising applications in optoelectronics.

Study of IGZO thin film transistors with Al2O3 gate insulator

In this study focuses on the dielectric layer materials of thin film transistors (TFTs). Gate oxide was deposited using a RF Magnetron Sputtering control system. The first studied the aluminium oxide (Al2O3) dielectric layer material deposited with different oxygen flow and annealed by the furnace tube. The study found that the properties of aluminium oxide (Al2O3) thin film transistors (TFTs) after furnace tube annealing reduced the interface trap density and the roughness of the thin film after annealing. The above dielectric layer is used to make thin film transistors (TFTs) with a bottom gate structure. The characteristics of thin film transistors (TFTs) are significantly improved by higher oxygen flow and additional thermal anneal. By analyzing the structure and electrical measurement of the thin film, the influence of the dielectric layer material on the thin film transistors (TFTs) is analyzed.

Abnormal Threshold Voltage Shift and Sub-channel Generation in Top-Gate InGaZnO TFTs under Backlight Negative Bias Illumination Stress

Previous reports on the top-gate IGZO thin-film transistors (TFTs) under negative bias illumination stress (NBIS) show a threshold voltage (VTH) shift to the left. However, in the present study, a right shift in VTH was observed in the reverse-sweep current–voltage (I–V) curves after applying NBIS to top-gate IGZO TFTs by a UV backlight. The hysteresis window of the forward and reverse sweep I–V curves widened with the increase in the stress time. The abnormal VTH shift and hysteresis-window increment are explained using an energy-band diagram. In addition, an abnormal gm peak appeared in the forward I–V curve after 2000 s of the backlight NBIS, which was verified by testing the devices with different dimensions. Silvaco TCAD simulation results indicated a strong electric field in the sidewall, confirming the generation of sub-channels. The comparison of the ΔVTH after UV backlight NBIS in three different devices suggested that the higher N2O/SiH4 flow rate and lower power deposition can produce a good quality buffer layer. A rapid examination of a buffer layer is possible using the backlight NBIS. In addition, the presence of H2 in the buffer layer was confirmed by the thermal desorption spectroscopy. Finally, the reliability of the devices can be enhanced by improving the modulation of the existing deposition process.