Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors

Abstract

Defect annihilation of the IGZO/SiO2 layer is of great importance to enhancing the bias stress stabilities of bottom-gate coplanar thin-film transistors (TFTs). The effects of annealing temperatures (Ta) on the structure of the IGZO/SiO2 layer and the stabilities of coplanar IGZO TFTs were investigated in this work. An atomic depth profile showed that the IGZO/SiO2 layer included an IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. Higher Ta had only one effect on the IGZO layer and SiO2 layer (i.e., strengthening chemical bonds), while it had complex effects on the interfacial mixing layer—including weakening M-O bonds (M: metallic elements in IGZO), strengthening damaged Si-O bonds, and increasing O-related defects (e.g., H2O). At higher Ta, IGZO TFTs exhibited enhanced positive bias temperature stress (PBTS) stabilities but decreased negative bias temperature stress (NBTS) stabilities. The enhanced PBTS stabilities were correlated with decreased electron traps due to the stronger Si-O bonds near the interfacial layer. The decreased NBTS stabilities were related to increased electron de-trapping from donor-like defects (e.g., weak M-O bonds and H2O) in the interfacial layer. Our results suggest that although higher Ta annihilated the structural damage at the interface from ion bombardment, it introduced undesirable defects. Therefore, to comprehensively improve electrical stabilities, controlling defect generation (e.g., by using a mild sputtering condition of source/drain electrodes and oxides) was more important than enhancing defect annihilation (e.g., through increasing Ta).