The source/drain electrodes in IGZO TFTs (thin-film transistors) can be direct metal overlapping the IGZO region. However, to achieve ohmic behavior with minimal resistance and ensure tolerance to overlay error, several microns of gate overlap is required. IGZO TFTs with self-aligned channel regions have advantages in reduced parasitic capacitance and stage delay, and a reduction in overhead real estate. Several techniques have been used to selectively form conductive IGZO regions including the introduction of hydrogen [1, 2], plasma exposure [3] and ion implantation [4, 5]. This work provides an interpretation of donor activation in self-aligned bottom-gate (SA-BG) IGZO TFTs with ion-implantation of boron (11B+) and argon (40Ar+) species as the source/drain treatment.Preliminary work investigated a top-gate electrode configuration, which served as the implant mask for the self-aligned strategy. These devices exhibited a significant left-shift in the ID-VGS transfer characteristics that was attributed to charge accumulation on the metal gate, subjecting the gate dielectric to a high electric field and the creation of ionized defects [5]. The bottom-gate implementation utilizes the opaque gate electrode as a mask for a through-wafer exposure of positive photoresist, providing a perfectly aligned implant mask that averted this charging mechanism. Both 11B+ and 40Ar+ implanted SA-BG devices exhibited electrical characteristics that were consistent with non-SA devices [6], with minimal impact of added series resistance. However, there were noted differences in the device operation that became pronounced following thermal stress treatments below 200 °C. Hypotheses in the mechanisms involved with donor activation have been developed from both similarities and differences in electrical behavior. Results suggest a defect-induced mechanism is responsible for implant activation with 40Ar+, whereas implant activation with 11B+ is attributed to the formation of an electrically active donor species involving chemical bonding. Examination of characteristics measured before and after applied thermal stress will be used to explain the interpretation, with the additional support of SIMS and XPS analysis.References H. Wu, H. H. Hsieh, C. W. Chien, and C. C. Wu, “Self-aligned top-gate coplanar In–Ga–Zn–O thin-film transistors,” J. Display Technol., vol.5, no. 12, pp. 515–519, Dec. 2009.H. Kang, I. Kang, S. H. Ryu, and J. Jang, “Self-aligned coplanar a-IGZO TFTs and application to high-speed circuits,” IEEE Electron Device Lett., vol. 32, no. 10, pp. 1385–1387, Oct. 2011.Park, I. Song, S. Kim, S. Kim, C. Kim, J. Lee, H. Lee, E. Lee, H. Yin, K. Kim, K. Kwon, and Y. Park, “Self-aligned top-gate amorphous gallium indium zinc oxide thin film transistors,” Appl. Phys. Lett., vol. 93, no. 5, p. 053501, Aug. 2008.Chen, W. Zhou, M. Zhang, M. Wong, and H. S. Kwok, “Self-Aligned Indium-Gallium-Zinc Oxide Thin-Film Transistor with Source/Drain Regions Doped by Implanted Arsenic”, IEEE Electron Device Lett., vol. 34, no. 1, pp. 60–62, 2013.R. Chowdhury, M.S. Kabir, R.G. Manley, & K.D. Hirschman, “Self-Aligned IGZO TFTs with Boron Implanted Source/Drain Regions”, ECS Transactions, 92(4), 135–142., Oct. 2019.S. Kabir, R. R. Chowdhury, R. G. Manley, and K. D. Hirschman, “Device Structure and Passivation Options for the Integration of Scaled IGZO TFTs,” ECS Trans., vol. 92, no. 4, pp. 143–151, 2019. Figure 1
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