Hot Carrier Reliability Research Articles

[formula omitted] IO buffer with [formula omitted] devices considering hot-carrier and gate-oxide reliability issues

This paper presents circuit for 2×VDD signaling I/O buffer to solve the gate-oxide and hot-carrier reliability issues without consuming any active static power. The design is verified for a range of loads varying from 4 pF to 200 pF with operating speed ranging from 12 Mbps to 500 Mbps. The proposed circuit is implemented in 16 nm FinFET technology using 1.8 V thick gate devices. The design can be used in any CMOS technology for 2×VDD signaling I/O buffer to reduce hot-carrier effect and to avoid gate-oxide reliability issues.

Improved Hot-Carrier Reliability of an Ultralow R ON,sp SOI-LDMOS by Linearly Doped Technology for Automotive Application

Improved Hot-Carrier Reliability of an Ultralow <i>R</i> _ON,sp SOI-LDMOS by Linearly Doped Technology for Automotive Application

DC to AC analysis of HC vs. BTI damage in N-EDMOS used in single photon avalanche diode cell

N-channel Extended Drain Metal Oxide Semiconductor (EDMOS) device is analysed through its sensitivity to Hot-Carrier (HC), hot hole (HH) injections and Positive Bias Temperature (PBT) instability degradation using accelerated DC to AC lifetime technique. EDMOS device is optimized for an effective gate-length Leff = 0.25 μm, with a gate-oxide thickness Tox = 5 nm operating at a frequency of 3 MHz at nominal supply voltage VDD = 5 V. The device is used in a mixed structure dedicated to 3D integration of Single Photon Avalanche Diode (SPAD). We show that HC reliability of EDMOS transistor can be obtained using worst-case DC accelerating degradation at high temperature transferred to the real AC waveforms applied to N-channel device placed into the SPAD cell. This allows to deduce the AC device lifetime obtained from DC stressing using a quasi-static approach considering the dominant degradation mechanism at condition of maximum gate-voltage VGSmax. This is explained by the optimized structure in Tox, VDD and lateral isolation where PBT, Off mode and recovery effects have limited impacts during switching operation of the N-EDMOS device used in SPAD circuit environment.

Stably Saturated Output Current Characteristics and Hot-Carrier Reliability of a-InGaZnO Thin-Film Transistors With Source-Connected Field Plate

Stably Saturated Output Current Characteristics and Hot-Carrier Reliability of a-InGaZnO Thin-Film Transistors With Source-Connected Field Plate

Nonconducting RF and DC Hot Carrier Stresses in 14/16-nm FinFETs for RF Power Amplifiers

Hot carrier reliability under nonconducting (NC) RF and dc stresses is measured and modeled on 14/16-nm FinFETs used for RF PAs. The impact of stress on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textbf{I}-\textbf{V}$</tex-math> </inline-formula> and RF parameters is examined. RF parameter stress response suggests that degradations are located near the drain end of the channel within the pinch-off region. For classic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{gs}}=\text{0}$</tex-math> </inline-formula> V OFF-state RF stress, quasi-static-approximation (QSA) significantly underestimates degradation, necessitating measurement-based lifetime modeling. At near-threshold <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{gs}}$</tex-math> </inline-formula> , a condition of interest for our PAs, the degradation shows significant die-to-die variations dominated by variations of the subthreshold channel current that initiates the hot carriers. Modeling accounting for the subthreshold channel current variations shows that the near-threshold RF stress is approximately quasi-static. The results show that these FinFETs provide enough margins against NC RF stress for the intended PA applications.

Improving Hot Carrier Reliability of Organic-TFTs by Extended Electrode

This work investigates the impact of source-drain-gate electrode overlap geometry on the reliability of organic thin-film transistors (OTFTs). The degradation of electrical characteristics after stress-induced hot carrier instability (HCI) is analyzed by comparing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\text {D}}$ </tex-math></inline-formula> - <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {G}}$ </tex-math></inline-formula> transfer curves and C-V characteristic curves before and after the stress test. Severe degradation is observed in standard symmetry and source-extended structures, but increased reliability is observed in a drain-extended structure. A physical model is proposed to explain this behavior in the letter, and Technology Computer-Aided Design (TCAD) simulations are used to explore the electrical field distribution in the devices for further understanding.

Hot-carrier reliability and performance study of transistors with variable gate-to-drain/source overlap

Flexibility on the gate-to-drain/source overlap length is useful for selecting the best compromise between device performance (including short channel effects and gate scaling, ON-state current, parasitic overlap capacitance), and the device reliability to hot-carrier degradation. In this paper, the performance and reliability of transistors with variable overlap is studied in a 40 nm CMOS technology. A double-hump is observed in the substrate current characteristic in function of the gate voltage for low-overlap transistors. An analysis of the origin of the second substrate current hump is conducted, and it is attributed to impact ionization at the drain-side, source-side or both depending on the overlap. TCAD simulations are performed to explain the two possible origins of the double-hump characteristic, which are degradation of the gate control over the channel due to low overlap or hot-carrier trapping. Finally, electrical characterizations are conducted to measure the degradation rate for various overlap lengths. It is observed that a longer overlap gives the transistor a longer lifetime under hot-carrier stress conditions.

A physics-based drain current model for Si1-xGex source/drain NT JLFET for enhanced hot carrier reliability with temperature measurement

In this paper, we report, the hot carrier reliability issue in the Si1-xGex source/drain nanotube (NT) junctionless field-effect transistor (JLFET) with temperature variations. The surface potential, electric field and drain current have been formulated by developing a physics-based analytical model. SiGe in the source/drain regions creates valence band discontinuity of ΔEg = 0.23 eV which significantly increases the tunneling width at the channel/drain interface and therefore, results in a diminished L-BTBT action. The results demonstrate that at T = 500 K, drain current with the influence of interface trap charges in the Si1-xGex S/D architecture shows better immunity than the conventional NTJLFET. The Si1-xGex S/D enhances the reliability of analog/RF parameters such as transconductance (gm), intrinsic gain (gm/gd), cut-off frequency (fT), and gain-transconductance-frequency-product (GTFP), against the hot carriers. We have also explored the reliability with germanium (Ge) content, x and observed that for Ge content above x = 0.3, the reliability degrades in terms of higher electron temperature, reduced gm, and lower fT. The analytical results are verified and are in good agreement with results of Sentaurus TCAD simulations. The Si1–xGex S/D architecture combined with NT core gate can help relieve the HCI trap charge reliability for JLFETs leading to significantly improved analog/RF parameters.

Improving Drain-Induced Barrier Lowering Effect and Hot Carrier Reliability With Terminal via Structure on Half-Corbino Organic Thin-Film Transistors

This study proposes a terminal via structure for half-Corbino organic thin-film transistors (OTFTs) to improve drain-induced barrier lowering (DIBL) effect and reliability. A sub-channel conduction and DIBL phenomenon due to high drain voltages are observed on the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{{\text {D}}} - \text{V}_{{\text {G}}}$ </tex-math></inline-formula> curves of traditional half-Corbino OTFTs. The device breaks down at a drain voltage of −40 V. This is attributed to the strong electric field between the source/drain corner edge, which is verified by a COMSOL electric field simulation. The degradation behavior is inhibited through the terminal via structure. In addition, the terminal via structure reduces the on-current degradation by dispersing heat near the corner edge after the hot carrier effect.

Hot carrier reliability assessment of vacuum gate dielectric trench MOSFET (TG-VacuFET)

Hot carrier reliability assessment of vacuum gate dielectric trench MOSFET (TG-VacuFET)

A Thermal Circuit Representing Frequency Dependent Dynamic Heating Between Electron and Lattice in SOI-FinFET

A thermal circuit model that represents dynamic heating between electron and lattice at different frequencies has been demonstrated here. The model is effective for circuit based predictive simulations of the phenomenon as found in scaled metal-oxide-semiconductor field effect transistor (MOSFET), where electron heating substantially impacts its electrical characteristics including hot carrier reliability. High field or frequencies of the input signal as in the case of radio frequency (rf) MOSFET restrict heat transfer from electron to the lattice due to weak energy relaxation via low energy acoustic phonons, as a result soon a thermal non-equilibrium is established whose thermal equivalent circuit representation is not known until now. T-CAD based hydrodynamic-thermodynamic (HD-TD) modeling though can extract electron and lattice temperatures employing their detail energy balance relations, yet its numerical solver is cumbersome. In this context, we found that numerical complexities can be reduced without compromising generality, if heating between electron and lattice would be represented by an equivalent thermal circuit model with physically justified circuit elements, which would be valid over a frequency band of the input signal till the isothermal frequency where self-heating is a concern. In this context, from detail thermodynamic principle we calculated electron thermal capacitance, resistance and thermal inductance those were incorporated to the existing standard thermal circuit model. The new model was furthermore validated employing a calibrated 14 nm SOI-FinFET.

Comparative Performance and Reliability Analysis of Doping and Junction Free Devices with High-κ/Vacuum Gate Dielectric

A comparative evaluation of channel hot carrier (CHC) reliability and pursuance of dopingless FET (DL JLFET) and junctionless FET (JLFET) are studied for various dielectrics and compared with conventional dielectric (SiO2) JLFET. The use of dielectrics such as vacuum near the drain and the high-κ (HfO2) near the source in DL JLFET (VacuHDL JLFET) allows better pursuance and reliability against channel hot carrier (CHC) effects. A simulation study has shown that the pursuance of VacuHDL in terms of Ion/Ioff ratio is improved by 4.5, 19.38 and 39.58 times, respectively, in comparison with vacuum based DL, HJL and JL. Similarly, the intrinsic delay of VacuHDL is improved by 9.5%, 56.8% and 58.7%, respectively, in comparison with VacuDL, VacuHJL and VacuJL. Hence, VacuHDL is a potential candidate for digital circuit applications. Further, we have found that vacuum-based HDL and HJL are more immunes against CHC stress and shown that the drain current of vacuHDL and vacuHJL is reduced by 6.9% and 17.5%, respectively, in comparison with conventional dialectic (SiO2) based DL and JL which is 10.4% and 20.5%. Hence, the incorporation of vacuum dielectric towards drain terminal is helpful in reducing CHC induced effect in comparison with conventional dielectric.

TID Response and Radiation-Enhanced Hot-Carrier Degradation in 65-nm nMOSFETs: Concerns on the Layout-Dependent Effects

Layout dependence of total-ionizing-dose (TID) response, hot-carrier degradation (HCD), and radiation-enhanced HCD (REHCD) in 65-nm bulk Si nMOSFETs are experimentally investigated in this article. For TID response, the average irradiation-induced V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift slightly increases by several millivolts with increasing gate-to-active area spacing (SA), which is contrary to the trend previously observed in pMOSFETs. HCD is much more severe in irradiated devices and the average hot-carrier-stress-induced V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift continuously decrease with increasing SA for both irradiated and unirradiated devices, indicating potential better hot-carrier reliability with larger SA. Finally, layout dependence of REHCD is illustrated. REHCD is enhanced with increasing SA, which may reduce the reliability improvement of irradiated devices with larger SA. These layout dependencies are attributed to larger tensile strain in the channel. The results provide early insights into the layout dependence of TID effects and HCD, highlighting potential concerns on the reliability of devices working in radiation environment.

Hot-Carrier-Induced Reliability for Lateral DMOS Transistors With Split-STI Structures

In this work, four kinds of lateral double-diffused MOS (LDMOS) devices with different split shallow trench isolation (STI) structures (Device A: LDMOS with traditional split-STI, Device B: LDMOS with slope-STI, Device C with step-STI and Device D with H-shape-STI) have been fabricated and the hot-carrier reliabilities also have been investigated due to the serious environment they are endured. The maximum bulk current (Ibmax) stress and the maximum gate voltage (Vgmax) stress have been carried out and the inner mechanism of device degradation have been investigated successfully. With the assistance of the T-CAD simulation tools, it is found that the main damage point locates at the STI conners with a mount of interface states generation, inducing serious degradation for these four devices. The Device D owns high hot-carrier reliability due to its special structure with narrow split-STI. The worst device is Device C because of the presence of extra STI damage point. Finally, a mechanism verification, the charge pumping (CP) method has been applied to better understand this work.

A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors

In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design/layout. Through proper device design, fabrication and measurement on different test structures, we have shown that the graded channel significantly improves the drive capability (upto ~30%), analog FoMs and hot-carrier reliability of LDMOS transistors without any penalty on the OFF-state performance. The performance improvement is independent of drift region design (breakdown voltage). The device physics behind different observations is also discussed with detailed TCAD simulations.

Enhancing Hot-Carrier Reliability of Dual-Gate Low-Temperature Polysilicon TFTs by Increasing Lightly Doped Drain Length

In this article, an n-type double-gate low-temperature polysilicon (LTPS) TFT is investigated. Previous work has confirmed that the hot-carrier effect will cause impact ionization. Here we observed that, after hot-carrier stress (HCS), the transfer curve in the saturation region has a negative Vth shift, and a hump is also observed. The reverse output characteristic shows that gate induced drain leakage (GIDL) of the transistor gradually increases and the subthreshold swing (S.S.) has a tendency to collapse. In structures with longer lightly doped drain (LDD) lengths, the electric field at both source/drain side can be effectively dispersed. Thereby, an extended LDD can reduce the overall degradation, and a physical model of explanation is proposed. By using the energy band diagram, we clarify how the additional electron hole pairs affect the output property. Next, Silvaco TCAD simulation is utilized to illustrate the electric field distribution and validate the physical model.

Engineering Schemes for Bulk FinFET to Simultaneously Improve ESD/Latch-Up Behavior and Hot Carrier Reliability

This article presents a simultaneous impact of selective contact silicidation, silicide, and junction engineering on bulk FinFET’s electrostatic discharge (ESD) reliability, latch-up (LU) robustness, and hot carrier-induced (HCI) degradation. The investigations are performed using 3-D TCAD simulations. To maximize the robustness against HCI reliability and to improve the ESD/LU performance simultaneously, essential technology guidelines are derived based on physical insights developed. With the incorporation of proposed S/D contact silicide and junction engineering, the ESD robustness of FinFETs can be improved by a factor of $6\times $ compared to conventional approaches. Besides, this is found to improve the overall HCI reliability of bulk FinFETs. Based on these design guidelines, hybrid contact/junction engineered scheme is proposed for the overall robustness of FinFET system-on-chips (SoC).

Characterization and Modeling of Hot Carrier Degradation in N-Channel Gate-All-Around Nanowire FETs

In this article, we present a detailed analysis of the dependence of hot-carrier (HC) induced damage on the device design parameters in silicon-on-insulator (SOI) gate-all-around (GAA) nanowire (NW) n-field-effect transistors (FETs). Particularly, the HC reliability of NWs at extremely small (5 nm) to large (40 nm) widths is assessed for devices with different gate lengths. A substantial improvement in device reliability is observed at smaller NW widths, which could be due to the quantization effects and reduced effective stress voltages due to the increase in source/drain resistance. The difference in prestress device parameters, such as threshold voltage and source/drain resistance, is shown to affect the HC degradation (HCD) by altering the actual stress voltages applied to the device. Further, the impact of self-heating on the HCD mechanism is studied for devices with different fin density and gates per active region. Consequently, an empirical model is extracted using the measurement results where the empirical prefactors accurately capture the degradation in deeply scaled GAA-NWFETs.

Investigation of Hot-Carrier Degradation in 0.18-$\mu$ m MOSFETs for the Evaluation of Device Lifetime and Digital Circuit Performance

In this work, we investigate the hot-carrier reliability in $0.18{\mu}\text{m}$ MOSFET technology that is being extensively employed in various analog/digital applications. Hot-carrier degradation in MOSFETs is known to follow power-law relation where the time exponent of the degradation curve can be utilized to quantify the device ageing. Here, we examine the dependency of time power-law exponent on different gate stress bias to determine the physical mechanism responsible for device degradation. Extensive consideration is given to the maximum impact ionization condition Vgs = Vds/2 and maximum hot-electron injection condition Vgs = Vds . Time evolution of degradation curve depicts changing slope with increasing stress duration. This variation in time power-law exponent over different stress time intervals is an important indicator of changing degradation mechanism as the device ages. Since the operating conditions for a device directly relates to its targeted application, therefore DC lifetime prediction under the influence of different Vgs/Vds stress bias combinations is performed to determine the limiting case challenging the circuit integrity. Also, the impact of hot-carrier degradation on the circuit delay under the aforementioned stress conditions is evaluated for typical digital CMOS circuits. Effective switching current methodology is employed for the delay analysis in transistor stacks that comprise inverter, NAND, and NOR circuits to show the adverse effects of the damage caused by the hot-carriers.

Hot carrier instability associated with hot carrier injection and charge injection in In0.7Ga0.3As MOSFETs with high-κ stacks

Channel hot carrier (CHC) reliability in In0.7Ga0.3As nMOSFETs with Al2O3/HfO2 (EOT = 0.8 nm) during CHC stress has been studied in scaled-down gate devices. The threshold voltage degradation (ΔVT) during CHC stress was attributed to the hot carrier injection into Al2O3 or/and HfO2 defect sites, rather than charge trapping into high-κ bulk defects. Additionally, with an increase of gate voltage at a fixed drain voltage (VDS), there was an increase in probability that the InGaAs channel carriers are easily injected into Al2O3 or/and HfO2 defect sites, causing the worst ΔVT degradation at the same VGS = VDS stress condition. Hence, hot carrier injection during CHC stress was divided into two components: charge injection by the vertical field near the source region and injection of hot carriers into the oxide bulk defects at the drain corner. To decouple the charge trapping and hot carrier injection into the gate oxide defect sites during CHC stress, an unrecovered (hot carrier damage) and recovery ratio (charge injection) of the ΔVT degradation after relaxation and opposite polarity voltage were calculated to be about ∼70% and ∼30%, respectively. Therefore, hot carrier injection has emerged as a dominant degradation factor in InGaAs MOSFETs with high-κ dielectrics.