Abstract
This work investigates the impact of source-drain-gate electrode overlap geometry on the reliability of organic thin-film transistors (OTFTs). The degradation of electrical characteristics after stress-induced hot carrier instability (HCI) is analyzed by comparing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\text {D}}$ </tex-math></inline-formula> - <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {G}}$ </tex-math></inline-formula> transfer curves and C-V characteristic curves before and after the stress test. Severe degradation is observed in standard symmetry and source-extended structures, but increased reliability is observed in a drain-extended structure. A physical model is proposed to explain this behavior in the letter, and Technology Computer-Aided Design (TCAD) simulations are used to explore the electrical field distribution in the devices for further understanding.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
