DC to AC analysis of HC vs. BTI damage in N-EDMOS used in single photon avalanche diode cell

Abstract

N-channel Extended Drain Metal Oxide Semiconductor (EDMOS) device is analysed through its sensitivity to Hot-Carrier (HC), hot hole (HH) injections and Positive Bias Temperature (PBT) instability degradation using accelerated DC to AC lifetime technique. EDMOS device is optimized for an effective gate-length Leff = 0.25 μm, with a gate-oxide thickness Tox = 5 nm operating at a frequency of 3 MHz at nominal supply voltage VDD = 5 V. The device is used in a mixed structure dedicated to 3D integration of Single Photon Avalanche Diode (SPAD). We show that HC reliability of EDMOS transistor can be obtained using worst-case DC accelerating degradation at high temperature transferred to the real AC waveforms applied to N-channel device placed into the SPAD cell. This allows to deduce the AC device lifetime obtained from DC stressing using a quasi-static approach considering the dominant degradation mechanism at condition of maximum gate-voltage VGSmax. This is explained by the optimized structure in Tox, VDD and lateral isolation where PBT, Off mode and recovery effects have limited impacts during switching operation of the N-EDMOS device used in SPAD circuit environment.