Engineering Schemes for Bulk FinFET to Simultaneously Improve ESD/Latch-Up Behavior and Hot Carrier Reliability

Abstract

This article presents a simultaneous impact of selective contact silicidation, silicide, and junction engineering on bulk FinFET’s electrostatic discharge (ESD) reliability, latch-up (LU) robustness, and hot carrier-induced (HCI) degradation. The investigations are performed using 3-D TCAD simulations. To maximize the robustness against HCI reliability and to improve the ESD/LU performance simultaneously, essential technology guidelines are derived based on physical insights developed. With the incorporation of proposed S/D contact silicide and junction engineering, the ESD robustness of FinFETs can be improved by a factor of $6\times $ compared to conventional approaches. Besides, this is found to improve the overall HCI reliability of bulk FinFETs. Based on these design guidelines, hybrid contact/junction engineered scheme is proposed for the overall robustness of FinFET system-on-chips (SoC).