Hot-carrier Degradation Mechanisms Research Articles

Re-Examination of Hot Carrier Degradation Mechanism in Ultra-Scaled nFinFETs

In this study, the channel length dependence of hot carrier degradation (HCD) in ultra-scaled nFinFETs is experimentally investigated with the self-heating correction. By electrical characterizations of nFinFETs with different channel lengths, the novel insight into the HCD mechanism is proposed upon considering the trap behaviors, including both interface traps and oxide traps. Our experimental results show that the proportion of interface traps in total traps is strongly dependent on the channel length. Furthermore, the interface traps induced by HCD are located near the source side in ultra-scaled nFinFETs, which is different from the phenomena in long channel devices.

Overview of Aging Mechanisms in Sige Hbts

This paper reviews the recent studies in hot carrier degradation mechanisms of SiGe HBTs under saturation mode and off-state operation. Reliability of these devices gets increased scrutiny as technological scaling drives down device dimensions. Even as the performance of these devices increases, the hot carrier generation and reaction kinetics concepts driving degradation in sensitive regions of the device remain the same. The new mechanisms discussed here can be broadly categorized using the physics of high-voltage or high-current electrical stress conditions that have been well-studied. Measurements and TCAD simulations suggest that voltage-limited mechanisms consistently see worse degradation at lower temperatures while current-limited mechanisms respond to both higher temperature and higher current density. These limitations must be carefully evaluated during the development of new technologies and circuits.

TCAD simulation of hot-carrier stress degradation in split-gate n-channel STI-LDMOS transistors

A combined experimental and simulation analysis of the degradation mechanisms induced by hot carriers in a silicon-based split-gate n-channel LDMOS transistor featuring an STI structure is reported. In this regime, electrons can gain sufficient kinetic energy necessary to create charged traps at the silicon/oxide interface, thus inducing device degradation and causing the shift of the electrical parameters of the device. In particular, the on-resistance degradation in linear regime has been experimentally characterized at different stress conditions and at room temperature. The hot-carrier degradation has been reproduced in the frame of TCAD simulations by using physical-based models aimed at reproducing the degradation kinetics. An investigation of the electron distribution function at different stress conditions and its dependence on the split-gate bias is carried out achieving a quantitative understanding of the role played by hot electrons in the hot-carrier degradation mechanisms of the device under test.

Characterization and Modeling of Hot Carrier Degradation in N-Channel Gate-All-Around Nanowire FETs

In this article, we present a detailed analysis of the dependence of hot-carrier (HC) induced damage on the device design parameters in silicon-on-insulator (SOI) gate-all-around (GAA) nanowire (NW) n-field-effect transistors (FETs). Particularly, the HC reliability of NWs at extremely small (5 nm) to large (40 nm) widths is assessed for devices with different gate lengths. A substantial improvement in device reliability is observed at smaller NW widths, which could be due to the quantization effects and reduced effective stress voltages due to the increase in source/drain resistance. The difference in prestress device parameters, such as threshold voltage and source/drain resistance, is shown to affect the HC degradation (HCD) by altering the actual stress voltages applied to the device. Further, the impact of self-heating on the HCD mechanism is studied for devices with different fin density and gates per active region. Consequently, an empirical model is extracted using the measurement results where the empirical prefactors accurately capture the degradation in deeply scaled GAA-NWFETs.

Reliability Modeling and Analysis of Hot-Carrier Degradation in Multiple-Fin SOI n-Channel FinFETs With Self-Heating

A comprehensive study on hot-carrier degradation (HCD) mechanisms in 14 nm silicon-on-insulator (SOI) n-channel FinFETs is presented. The impact of high-frequency AC stress bias on self-heating (SH) enhanced hot-carrier injection in oxide bulk traps is investigated and compared with the measurement results using the conventional DC stress bias. The influence of SH on electrical parameter degradation due to hot-carriers is shown as an important metric for accurate device reliability analysis. The relative contribution of bulk and interface traps is determined to identify the dominant mechanism responsible for HCD for different device geometries. The device behavior is thoroughly studied under hot-carrier DC and AC stresses for different device design parameters, such as effective oxide thickness, number of fins, and channel length. Based on measured data, we have proposed an empirical model for reliability degradation, which takes into account some of the key device design parameters and stress bias frequency.

Microscopic Hot-Carrier Degradation Modeling of SiGe HBTs Under Stress Conditions Close to the SOA Limit

We present and validate a physics-based model to describe the underlying mechanisms of hot-carrier degradation in bipolar transistors. Our analysis is based on a deterministic solution of the coupled system of Boltzmann transport equations for electrons and holes. The full-band transport model provides the energy distribution functions of the charge carriers interacting with the passivated Si–H bonds along the oxide interface. The simulation results assert the dominant role of hot holes along the emitter–base spacer oxide interface in the long-term degradation of an n-p-n SiGe heterojunction bipolar transistor under low and high-current conditions at the border of the safe-operating area. The interface trap density is calculated by incorporating an energy driven paradigm for the microscopicmechanisms of defect creation into a reaction-limitedmodelwith dispersive reaction rates. These interface traps increase the forward-mode base current via Shockley–Read–Hall recombination and degrade the overall device performance. The Gummel characteristics of a degraded device and time evolution of the excess base current for different stress conditions are verified versus the experimental data obtained for a state-of-the-art toward-terahertz SiGe HBT.

Hot carrier degradation mechanism interpretation by lateral distribution of interface and bulk trap density

We investigated the drain avalanche hot carrier effect (DAHC) of p-type metal-oxide-semiconductor field effect transistor of 0.14 μm channel length (PMOSFET) with SiON gate dielectric. Using three different stress conditions of substrate maximum current, the changes to threshold voltage, maximum transconductance, saturation current and channel leakage current was monitored. Concurrently, the lateral distribution of interface trap density (Nit) and bulk trapped charge density (Not) with stress time has been extracted along the 70 nm half channels from gate edge to drain junction, which is the first endeavor in describing charge traps along sub 100 nm short channels. The degradation of the PMOSFET was described by combining electrical property with Nit and Not profiles. Hot electron punch through (HEIP) effect was evidenced by negative Not distribution near the drain junction while more severe hot carrier degradation was successfully demonstrated by the empirical power law dependence of the electrical parameters Nit and Not. We have studied the evolution of degradation behavior along highly scaled tens of nanometer channel, and Nit and Not profile offers systematic study and interpretation of degradation mechanism of hot carrier effect in MOSFET devices.

Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$-FinFETs

The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (VG ~ VD/2). At higher VG closer to VD, cold and hot carrier injection to the oxide bulk defect increases and dominates at the VG=VD stress condition. On the other hand, in short channel devices, hot carriers are generated continuously with respect to VG and highly at VG=VD, and this hot carrier injection into the oxide bulk defect is the main degradation mechanism.

Voltage dependences of parameter drifts in hot carrier degradation for n-channel LDMOS transistors

• We evaluate the hot carrier degradation mechanisms for n-channel LDMOS transistor with STI based structures. • The slope of I D,lin degradation indicates the different degradation mechanism under various bias stress. • The location of peak impact ionization differs at various V GS stress but consistent at various V DS stress. • The degradation mechanism is highly dependent on the stress voltage at the gate ( V GS ). • The V DS is found as an accelerating factor for the hot carrier stress test. The reliability characterization in shallow trench isolation (STI) based n-channel lateral diffused metal–oxide–semiconductor (LDMOS) transistor has recently drawn much attention. A thorough investigation of the hot carrier degradation under various gate and drain stress biases are carried out to gain an insight on the bias dependences of the parameter drifts. The findings are supported by both experimental and the technology computer-aided design (TCAD) simulations data. Based on the results, the drain voltage ( V DS ) parameter was found as a significant accelerating factor for the test. The analysis of HCI damage phenomenon on this device shows that the degradation mechanism is highly dependent on the stress voltage at the gate ( V GS ).

Model of hot‐carrier degradation for lateral IGBT device on SOI substrate

A novel model for hot-carrier degradation in a lateral insulated gate bipolar transistor (IGBT) device on SOI substrate (SOI-LIGBT) is presented. The setup of the model is based on the existing hot-carrier degradation mechanism in a SOI-LIGBT and assisted by a lateral DMOS device on SOI substrate (SOI-LDMOS) with completely the same structure except for the doping type in the drain area. The model parameters have been extracted by the degradation measurement results and the validity of the proposed model in a SOI-LIGBT has been also verified.

Hot-carrier degradation mechanism for p-type symmetric LDMOS transistor with thick gate oxide

Hot-carrier-induced degradation in the p-type symmetric lateral DMOS transistor (ps-LDMOS) with thick gate oxide has been experimentally investigated. It is noted that only one peak bulk current is observed for different Vgs owing to the Kirk effect hardly happening in the ps-LDMOS. Experimental results also show that interface state generates in the channel and p-drift regions; however, hot electron injection and trapping into the oxide of the p-drift region dominates the degradation, leading to the on-resistance (Ron) decrease. Moreover, no hot-carrier injection is found in the channel region. Charge pumping measurements and T-CAD simulations have been performed to verify the experimental findings.

Novel Hot-Carrier Degradation Mechanisms in the Lateral Insulated-Gate Bipolar Transistor on SOI Substrate

The different hot-carrier degradation mechanisms of the lateral insulated-gate bipolar transistor on a silicon-on-insulator substrate (SOI-LIGBT) for different stress conditions have been experimentally investigated for the first time. For low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> and high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> , the hot hole injects and traps into the accumulation and the field oxide, particularly the bird's beak, which results in the decrease in the on-resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> at the early stress stage. It is interesting that the decrease level of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> in SOI-LIGBT is much more serious than that in the SOI laterally diffused metal-oxide-semiconductor with the same structure fully except for the doping type in the drain area. In addition, the buried oxide surface under the drain area also suffers from severe hot-carrier degradation. However, for high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> and low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> , only hot-electron injection into the gate oxide near the source side can be observed; there is no hot-carrier degradation to be found in both the field and buried oxides.

Hot-Carrier Degradation in Low-Temperature Polycrystalline Silicon n-Channel Lightly Doped Drain Thin-Film Transistors

The hot-carrier degradation mechanism in low-temperature polycrystalline silicon (poly-Si) n-channel lightly doped drain (LDD) thin-film transistors (TFTs) is investigated. The degradation is characterized by transconductance degradation (ΔGm) at low drain voltage (Vd) and decreases in substrate current (Isub) and kink current at high Vd. It is assumed that the trapped negative charges (acceptor-type trap states) in the gate edge region, mostly outside and partly inside the gate, contribute to hot-carrier degradation after stress under current saturation bias. The degradation presumably first occurs outside the gate in the LDD region and, with increasing stress time, the electron-trapped region expands toward the channel under the gate owing to the saturation of electrons in the trap states. At high-Vd bias, a decrease in the lateral electric field in the gate-edge region due to the presence of negative charges reduces Isub and the drain current Id, thereby reducing the kink current. At low-Vd bias, the current flow near the upper interface in the gate-edge region decreases after the stress owing to the generated negative charges. The negative charges lead to the decrease in Id in the deep-gate voltage Vg region in Vg–Id characteristics.

Investigation of hot carrier degradation in asymmetric nDeMOS transistors

Abstract Hot carrier degradation in asymmetric nDeMOS transistors is investigated in this paper. It is found that the worst case hot carrier stress condition in asymmetric nDeMOS transistors is at Ig,max, and not at Ib,max and hot-electron injection (HE, i.e. Vgs = Vds). Further, the damage regions in transistors upon various hot carrier stress modes are located by using variable amplitude charge pumping technique. It is found that the interface traps generation in the gate/n-type graded drain (NGRD) overlap and spacer/NGRD regions is the dominant mechanism of hot carrier degradation in transistors upon Ig,max stress mode. Moreover, both the interface trap generation and the electron trapping are two important factors to induce the electrical parameters shifts of asymmetric nDeMOS transistors under Ib,max and HE stress.

Locating hot carrier degradation in asymmetric nDeMOS transistors by gated diode technique

In this paper, hot carrier degradation in asymmetric nDeMOS transistors is investigated. For the first time, we found that the worst hot carrier stress condition is at Ig,max, and not at Ib,max and HE stress conditions. The damage regions in transistors upon various hot carrier stress modes are located by using gated diode technique. It is found that the interface traps generation in the gate/n-type graded drain (NGRD) overlap and spacer oxide regions is the dominant mechanism of hot carrier degradation in asymmetric nDeMOS transistors upon various hot carrier stress modes. Furthermore, the bulk silicon damages locating at the p-well and NGRD regions during hot carrier stress must be taken into account, because they lead to a series of issues, such as the increase in Ioff current, the off-state breakdown voltage decrease, and so on.

Degradation mechanism understanding of NLDEMOS SOI in RF applications

The distinct channel hot-carrier (CHC) degradation mechanisms have been observed in NLDEMOS processed from a SOI CMOS technology. The charge-pumping (CP) technique has evidenced the larger hot-hole efficiency in the damage mechanisms at maximum substrate current condition where a net hole trapping is observed in the overlap region which is further screened by the large increase of interface traps in this region. As a consequence, the device suffers from a mobility reduction due to the series-resistance increase mostly in linear mode which impacts the device speed response to AC signal. Off state stressing exhibits a very similar CHC degradation behavior due to the interface traps which may represents a limitative case for the pulses shape optimisation encountered in Class-E operation. A modified reaction-diffusion modelling is proposed based on the multi-vibrational hydrogen release mechanism which matches the time dependence and saturation effect. Finally, we show that the efficiency of E-Class power amplifier is weakly affected by the series-resistance degradation.

Parasitic S/D resistance effects on hot-carrier reliability in body-tied FinFETs

Hot-carrier effects (HCEs) in fully depleted body-tied FinFETs were investigated by measuring the impact-ionization current. To understand the hot-carrier degradation mechanism, stress damages were characterized by dc hot-carrier stress measurement for various stress conditions and fin widths. The measurement results show that the generation of interface states is a more dominant degradation mechanism than oxide-trapped charges for FinFETs with a gate-oxide thickness of 1.7 nm. It was found that a parasitic voltage drop due to a significant source/drain extension resistance plays an important role in suppressing the HCEs at narrow fin widths. This letter can provide insight determining the worst stress condition for estimating the lifetime and optimizing between reliability and ON-state drain-currents.

Superior hot carrier reliability of single halo (SH) silicon-on-insulator (SOI) nMOSFET in analog applications

In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output characteristics and experimental characterization results on these devices show better V/sub th/-L roll-off, low DIBL, higher breakdown voltages, and kink-free operation. Further SH SOI MOSFETs have been shown to exhibit reduced parasitic bipolar junction transistor effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance, and better dynamic intrinsic gain (g/sub m/R/sub o/) in comparison with the conventional homogeneously doped SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device simulations, the lower hot carrier degradation mechanism in SH SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs.

Hole injection enhanced hot-carrier degradation in PMOSFETs used for systems on chip applications with 6.5–2 nm thick gate-oxides

Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide ( T ox=2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above −1.8 V. Devices with T ox=6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging–discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.

Buried channel silicon-on-insulator MOSFETs for hot-electron spectroscopy

Hot-carrier degradation in deep sub-micron MOSFETs can lead to shifts in the threshold voltage, reduction in effective mobility and transconductance, and reduced device reliability. Voltage and current stress measurements are often used to determine the hot-carrier degradation mechanisms. However, direct measurements of the hot-carrier distribution are difficult to make because the inversion layer in a conventional MOSFET is buried beneath the MOS gate material. In this paper, we describe a novel buried-channel silicon-on-insulator MOSFET that is suitable for hot-electron spectroscopy using a scanning-probe microscope.