Hot carrier degradation mechanism interpretation by lateral distribution of interface and bulk trap density

Abstract

We investigated the drain avalanche hot carrier effect (DAHC) of p-type metal-oxide-semiconductor field effect transistor of 0.14 μm channel length (PMOSFET) with SiON gate dielectric. Using three different stress conditions of substrate maximum current, the changes to threshold voltage, maximum transconductance, saturation current and channel leakage current was monitored. Concurrently, the lateral distribution of interface trap density (Nit) and bulk trapped charge density (Not) with stress time has been extracted along the 70 nm half channels from gate edge to drain junction, which is the first endeavor in describing charge traps along sub 100 nm short channels. The degradation of the PMOSFET was described by combining electrical property with Nit and Not profiles. Hot electron punch through (HEIP) effect was evidenced by negative Not distribution near the drain junction while more severe hot carrier degradation was successfully demonstrated by the empirical power law dependence of the electrical parameters Nit and Not. We have studied the evolution of degradation behavior along highly scaled tens of nanometer channel, and Nit and Not profile offers systematic study and interpretation of degradation mechanism of hot carrier effect in MOSFET devices.