Abstract
The interface and bulk trap densities were separately extracted from self-aligned top-gate (SA-TG) coplanar indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) using the low-frequency capacitance–voltage (C–V) characteristics and space-charge-limited current (SCLC) under the flat-band condition. In the method based on the C–V curve, the energy distribution of the interface trap density was extracted using the low-frequency C–V characteristics, and that of the bulk trap density was obtained by subtracting the density of interface trap states from the total subgap density of states (DOS) at each energy level. In the SCLC-based method, the energy distribution of the bulk trap density was extracted using the SCLC under the flat-band condition at high drain-to-source voltages, and that of the interface trap density was obtained by subtracting the density of bulk trap components from the total subgap DOS at each energy level. In our experiments, the two characterization techniques provided very similar interface and bulk trap densities and showed that approximately 60% of the subgap states originate from the IGZO/SiO2 interface at the conduction band edge in the fabricated IGZO TFTs, although the two characterization techniques are based on different measurement data. The results of this study confirm the validity of the characterization techniques proposed to separately extract the interface and bulk trap densities in IGZO TFTs. Furthermore, these results show that it is important to reduce the density of interface trap states to improve the electrical performance and stability of fabricated SA-TG coplanar IGZO TFTs.
Highlights
Since the first report in 2004, indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) have attracted significant attention owing to their excellent electrical properties, high uniformity, and easy fabrication processes [1]
It is very important to compare the values of the interface and bulk subgap density of states (DOS) obtained using different characterization techniques to confirm the validity of these techniques and the accuracy of the extracted trap densities
Similar to the results obtained from the C–V method in Figure 6b, Figure 8b shows that approximately 61% of the total subgap states are interface trap states at EC in the fabricated self-aligned topgate (SA-TG) coplanar IGZO TFT
Summary
Since the first report in 2004, indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) have attracted significant attention owing to their excellent electrical properties, high uniformity, and easy fabrication processes [1]. In TFTs fabricated with disordered semiconductors, such as IGZO, it is very important to obtain precise information about the subgap density of states (DOS) because it strongly affects the electrical properties and stabilities of TFTs [4,5]. It is very important to compare the values of the interface and bulk subgap DOSs obtained using different characterization techniques to confirm the validity of these techniques and the accuracy of the extracted trap densities. DOSs extracted using low-frequency C–V characteristics and the SCLC under the flat-band condition. Our experimental results demonstrate that the interface and bulk subgap DOSs extracted using the two different techniques exhibit very similar values.
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