Hot-carrier Degradation Mechanisms Research Articles

Study on the degradation induced by donor interface state in deep-sub-micron grooved-gate P-channel MOSFET’s

The degradation of electrical performance induced by interface states is one main reason for failure occurs in deep-sub-micron MOS devices. Especially for grooved-gate MOS devices, there are a large amount of interface states and flaw formed during the etching of concave. Based on the hydrodynamics energy transport model, using MEDICI simulator, the degradation induced by donor interface states is analyzed for deep-sub-micron grooved-gate PMOSFET’s with different channel doping densities and compared with that of corresponding conventional planar PMOSFET’s. The results also compared with that of degradation induced by acceptor interface states. The simulation results indicate that the degradation induced by same interface state density in grooved-gate PMOSFET’s is larger than that in planar PMOSFET’s, and in both structure devices, the impact of electron donor interface states on device performance is far larger than that of hole donor interface state. This work gives an useful insight of mechanism of hot-carrier degradation for grooved gate MOS devices and lays a solid foundation for grooved gate devices used in deep-sub-micron region VLSI practically.

Hot-carrier degradation mechanism in narrow- and wide-channel n-MOSFETs with recessed LOCOS isolation structure

Narrow-channel n-MOSFETs with recessed LOCOS (R-LOCOS) isolation structure exhibit less hot carrier-induced degradation than wide-channel n-MOSFETs, but the degradation mechanism of both devices is the same. This new finding Is explained by the fact that in deep submicron MOSFETs with ultra-thin gate oxide, the dominant factor deciding the degradation behavior in narrow- and wide-channel devices is the vertical electric field effect rather than the mechanical stress effect.

A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique

A novel simulation-independent charge pumping (CP) technique is employed to accurately determine the spatial distributions of interface (N/sub it/) and oxide (N/sub 0t/) traps in hot-carrier stressed MOSFETs. Direct separation of N/sub it/ and N/sub 0t/ is achieved without using simulation, iteration, or neutralization. Better immunity from measurement noise is achieved by avoiding numerical differentiation of data. The technique is employed to study the temporal buildup of damage profiles for a variety of stress conditions. The nature of the generated damage and trends in its position are qualitatively estimated from the internal electric field distributions obtained from device simulations. The damage distributions are related to the drain current degradation and well-defined trends are observed with the variations in stress biases and stress time. Results are presented which provide fresh insight into the hot-carrier degradation mechanisms.

Hot carrier degradation mechanisms in sub-micron p channel MOSFETs: Impact on low frequency (1/f) noise behaviour

In this work we present new results which illustrate the impact of hot carrier (HC) degradation on the low frequency (1/f) noise behaviour of submicron p channel MOSFETs. Submicron p channel MOSFETs were subjected to HC stress at a range of gate bias conditions, and the response of the low frequency noise was recorded. The results obtained are in marked contrast to the reported influence of HC stress on nMOSFETs 1/f noise, and indicate that the measurement of 1/f noise is a useful tool for investigating HC induced aging effects in submicron p channel devices. The significance of these results to the use of pMOSFETs in analog applications is briefly discussed.

New Insight into the Degradation Mechanism of Nitride Spacer with Different Post-Oxide in Submicron LDD n-MOSFET's

In this paper, the hot carrier degradation mechanisms in lightly-doped drain (LDD) n-MOS devices with silicon nitride spacer have been investigated. A low temperature chemical vapor deposited (CVD) SiO2 oxide is used as a post-oxide between source/drain surface and the nitride spacer. The gated-diode measurement in combination with the gate-induced drain leakage (GIDL) current measurement techniques have been used to analyze the stress-induced interface state and oxide charges. For the first time, it was found that the oxide charge but not the interface state generation in the post oxide will dominate the device drain current degradation. Moreover, the CVD post oxide with N2 annealing has been proposed which is able to effectively suppress the generation of oxide charges and significantly improve the device hot carrier reliability. The scaling of gate oxide thickness and the optimization of source/drain junction to improve the device reliability are also demonstrated.

Hot-carrier degradation mechanisms in silicon-On-Insulator MOSFETS

The structure, operation principles and basic characteristics of SOI MOSFETs are evoked, before focusing on the degradation aspects. The hot-carrier injection into the front gate oxide and buried oxide is discussed as a function of silicon film thickness, transistor configuration (n- or p-channel, inversion- or accumulation-mode), and stressing bias. The special phenomena involved in ultra-thin, fully-depleted SIMOX MOSFETs are compared to those governing partially-depleted and bulk-equivalent transistors. It is demonstrated that the coupling between back-interface defects and front channel properties is a unique and very challenging degradation feature in SOI. The road map to reach an accurate electrical image of the degraded transistor, by accounting for coupling effects or by avoiding them, is described. Although the aging mechanisms and investigation methods are more sophisticated than in bulk Si, the degradation of SOI MOSFETs does not appear to impede on the development of high performance, low-voltage ULSI SOI circuits.

A hot-carrier degradation mechanism and electrical characteristics in S/sup 4/D n-MOSFET's

A silicided silicon-sidewall source and drain (S/sup 4/D) nMOSFET is demonstrated and its hot carrier reliability is investigated for the first time. This S/sup 4/D nMOSFET exhibited high drain current and well-suppressed short channel effects concurrently. In spite of the impact ionization rate issue, the S/sup 4/D structure offers a major improvement in current and transconductance degradations as compared with the LDD structure. The mechanism of the improved hot carrier reliability is explained using a two-dimensional (2-D) simulation.

In-depth analysis of opposite channel based charge injection in SOI MOSFETs and related defect creation and annihilation

Extensive PISCES simulations, incorporating non-local effects are carried out to obtain an in-depth understanding of the recently observed opposite channel based charge injection in SOI MOSFETs [1]. This charge injection is then combined with basic transistor characteristics and charge pumping current measurements to study the hot carrier degradation mechanisms in a variety of SOI MOSFET's, and clarify the separate roles played by hot electrons and holes in the degradation. It is also used as the basis for the design of a new, SOI based flash memory cell.

How do hot carriers degrade n-channel MOSFETs?

Explores the mechanisms of hot carrier degradation in n-MOSFETs. In addressing the problem of hot carrier degradation, we examine the carrier injection process, whereby electrons and holes are injected into the oxide from the channel. Next, we'll look at the processes responsible for creating damage. Third, the impact of the damage on the MOSFET's terminal characteristics is deternined. Then the damage process is modeled. Finally, we'll address ways to reduce hot carrier degradation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Three hot-carrier degradation mechanisms in deep-submicron PMOSFET's

Hot-carrier degradation is mainly caused by negative oxide-charge generation in the present-day PMOSFET's. We present experimental evidence showing that two more degradation mechanisms are important in the case of deep-submicron PMOSFET's. Firstly, the generation of interface states is significant in the case of sub-half-micron PMOSFET's. It even limits the lifetime of surface-channel transistors. Secondly, the generation of positive oxide charge by holes influences the characteristics. The latter process has been established unambiguously for the first time in PMOSFET's. We measured the bias dependence, the length dependence, and the time dependence separately for all three microscopic degradation mechanisms. We calculated the influence of these three mechanisms on the transconductance degradation. Summation of the three effects yields an excellent description of the experimentally determined time dependence of PMOSFET degradation for many bias conditions and various transistor geometries with either nitrided or conventional gate oxide.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Positive oxide-charge generation during 0.25 /spl mu/m PMOSFET hot-carrier degradation

A new hot-carrier degradation mechanism becomes important in 0.25 μm PMOSFET's. Hot-hole injection generates positive oxide charge near the drain. We determine the time dependence and the oxide-thickness dependence and we show a considerable enhancement of this degradation mechanism for nitrided gate oxides. For many bias conditions and many geometries, the time dependence of PMOSFET degradation can be successfully described by a summation of the time dependences of three separate degradation mechanisms: generation of interface states, negative oxide charge and positive oxide charge.

PMOSFET hot-carrier damage: oxide charge and interface states

The hot-carrier degradation mechanism in PMOSFETs (p-channel metal-oxide-semiconductor field-effect transistors) is studied for three transistor types over ten orders of magnitude in time. The authors observe oxide charge and interface states separately by charge pumping. Degradation for various gate lengths at many gate and drain voltages is measured and interpreted consistently. Negative oxide charge and interface states are generated by electrons near the drain. This charge attracts an inversion layer that extends the drain and reduces the effective transistor length logarithmically in time, simultaneously preventing degradation of the transistor operation by the generated interface states. However, holes may generate interface states outside the drain extension, decreasing the transconductance with a power of time.

Effectiveness of N/sub 2/O-nitrided gate oxide for high-performance CMOSFETs

Summary form only given. High-quality thin SiO/sub 2/ films are strongly needed for advanced integrated circuits such as CMOSFETs and EEPROMs. It is found that N/sub 2/O-nitrided SiO/sub 2/ film is more useful than NH/sub 3/-nitrided SiO/sub 2/ or pure SiO/sub 2/ film for obtaining high-performance CMOSFETs. However, the mechanism of hot-carrier degradation of CMOSFETs with these oxide films has not been discussed. A detailed study is reported on hot-carrier-induced degradation phenomena in nitrided SiO/sub 2/ gate CMOSFETs. It is confirmed that N atoms in gate oxide films prevent the generation of interface traps for NMOSFETs and H atoms accelerate electron trapping for PMOSFETs. Therefore, N/sub 2/O-nitrided gate oxide film free from H atoms is effective for obtaining high-performance CMOSFETs. >

Understanding of the hot carrier degradation behaviour of MOSFET's by means of the charge pumping technique

In this paper the unique features of the charge pumping (CP) technique are reviewed and discussed with emphasis on their role in the evaluation and understanding of the effects and mechanisms of hot carrier degradation in MOSFET's.

A cross section of hot-carrier phenomena in MOS ULSI's

The state-of-the-art and future perspective of hot-carrier effects in MOS devices are discussed from the viewpoint of: (1) the AC versus DC hot-carrier degradation mechanism, (2) initial stage degradation, (3) a hot-carrier effect specific to p-channel MOSFET's, (4) new hot-carrier effects in the ∼ 0.3 ωm region, (5) hot-carrier resistant device structure, and (6) mechanical stress induced hot-carrier effects. In particular, new hot-carrier effects and/or phenomena which have not been clarified so far, will be focused on. Thus, such a deeper physical insight into hot-carrier effects as shown here and feedback of this knowledge to device structures and circuits are strongly required to realize the deep submicron MOS ULSI's.