Horizontal Current Bipolar Transistor Research Articles

The Effect of Collector Region Design on Large-Signal Performance of Horizontal Current Bipolar Transistor (HCBT)

The impact of collector region design on large-signal performance of horizontal current bipolar transistor (HCBT) technology is investigated by calibrated time-domain load-pull measurements. Three representative high-performance devices of the same geometry but with different collector doping profiles, namely, uniform, n-well, and low-doped, are subjected to large-signal measurements wherein the radio frequency (RF) time-domain waveforms of current and voltage are measured to facilitate the determination of the maximum output power for each device. The extensive measurements outline the boundaries of the maximum collector current and voltage swings at RF determining linear operating area, which are a result of the physical phenomena in the high-current and high-voltage regimes, namely, the Kirk effect and impact ionization, respectively. While the highest-doped n-well HCBT provides the highest output power of 25.3 dBm at 1-dB gain compression, and the lowest-doped HCBT enables a wideband match at the collector, the HCBT with a uniform doping profile provides a tradeoff between the output power and bandwidth of the output match. The results show the versatility of HCBT technology as an alternative to CMOS and/or sillicon–germanium (SiGe) large-signal RF circuits for the front-ends (FEs) in the sub-6 GHz wireless communications range.

(Invited) On the Potential of Lateral BJTs and SiGe HBTs in Advanced CMOS Technologies

State-of-the-art SiGe HBTs have achieved astonishing performance demonstrating record fT /fmax of 505/720 GHz in bipolar-only process [1] and fT /fmax in the 300-400 GHz range in the commercial BiCMOS technologies [2-4], making them suitable for RF and millimeter wave applications as well as for high-performance analog and mixed-signal circuits. A number of fabrication steps must be added to CMOS backbone technology to obtain such high-performance self-aligned SiGe HBTs that generally include at least two polysilicon layers, one or more epitaxial growths, deep trenches, multiple spacers and other isolation and/or sacrificial layers. Although SiGe HBTs can be implemented several technology nodes behind CMOS with competitive or better RF performance, the addition of those fabrication steps and lithography masks notably increases the cost of technology. Furthermore, high-breakdown voltage HBTs are beneficial for higher-swing applications, such as RF power amplifiers, and their fabrication with high-speed transistors in the same process usually requires various collector implantation schemes, increasing the number of added masks and steps further. Lateral bipolar transistors (LBTs) could principally provide a viable solution for a tradeoff between technological complexity and high-performance due their compact structure where intrinsic transistor regions are more easily accessible from the silicon surface. However, their electrical characteristics in pure-silicon are inferior to those of standard vertical-current transistors so far [5, 6]. As the most advanced lateral-current-flow device, Horizontal Current Bipolar Transistor (HCBT) (Fig. 1.a) [7] has optimum doping profile with low parasitics and is the highest-speed implanted-base Si BJTs, integrated with CMOS in low-cost technology and with the capability to adjust breakdown voltage without any increase in process complexity [8], just by layout manipulation. Due to lateral current flow, the electric field from collector can be shielded in various ways: by recessed CMOS p-well region (Fig. 1.b) increasing BV CEO above 10 V; by double emitter structure with BV CEO>12 V (Fig. 1.c); by double emitter structure with recessed p-well with BV CEO>36 V (Fig. 1.d); and by floating field plates with BV CEO>45 V (Fig. 1.e). Such a wide range of breakdown voltages in the same technology enables: (i) the implementation of high-voltage circuits currently covered by Bipolar-CMOS-DMOS (BCD) process in HCBT technology, (ii) integration of such high-voltage, i.e. power-management and/or analog circuits with RF circuits.The potential of HCBT concept with SiGe base is examined by TCAD simulations. SiGe base stack is placed on the sidewall of the active collector region, as shown in Fig. 2, instead of implanted intrinsic base. The extrinsic base p+ region is implanted into the top part of the grown stack. The electrical characteristics are consistently compared to the self-aligned vertical-current SiGe HBT with the geometry corresponding to the most advanced devices from literature (Fig. 3). Both structures have the same intrinsic doping profile, shown in Fig. 4. Since the extrinsic base overhangs the active collector region in HCBT introducing extrinsic C BC and affecting the collector current distribution, its doping profile shape critically impacts the high-frequency performance. The fT and fmax of the HCBT structure in Fig. 2 are similar to those of vertical current HBT with f T lower by 11 GHz and f max basically equal, whereas the HCBT with more realistic extrinsic base shape results in the improved fT /fmax up to 358/490 GHz (Fig. 5), without impacting β and BV CEO, as shown in Table I. Due to the one-sided base contact, HCBT has higher RB and lower CBC per emitter length and for a given IC HCBT has to be twice longer resulting in a smaller RB and a bit higher CBC than in vertical-current HBT. The interface resistance between the base polysilicon and intrinsic base in vertical-current HBTs is not accounted for in simulations, but has been identified as significant contributor to total RB [1,3]. This RB component is eliminated in SiGe HCBT since the extrinsic base is directly metal-contacted without p+ polysilicon, implying a further improvement of RB in favor of HCBT in actual devices. The fT /fmax can be increased by reducing wbext as can be expected in down-scaling, as shown in Fig. 6, reaching fT /fmax of 375/505 GHz for wbext =45 nm and converging to an ideal 1D transistor. Applying the same concept to SOI substrate, fT /fmax are decreased (Fig. 7) due to denser current distribution in collector boosting the Kirk effect and increasing RC .Simulation study clearly show that HCBT concept can provide state-of-the-art high-frequency performance with vertical-current HBTs as a reference, while implemented in lower-cost technology with simpler integration schemes, that include high-voltage transistors, with both bulk and SOI advanced CMOS. Figure 1

Measurement of RF Linear Operating Area of Bipolar Transistors

The methodology for the measurement of the knee voltage and maximum collector current for the linear operation of bipolar transistors is described and demonstrated on the horizontal current bipolar transistor (HCBT). Both limits are determined by measuring loadlines at 1-dB compression point (P1dB), wherein the hard-limiting nonlinearity occurs only in the positive half-wave of the collector current. The boundary defines the knee voltage, maximum collector current, and the transition between the two in which the onset of the Kirk effect takes place. It is found that the maximum collector current boundary saturates at a constant value for higher collector-emitter voltages and that there are the optimum load impedance and bias point for the maximum output power in the linear regime. They are found for HCBT, which achieves the output power of 21.25 dBm (P1dB) at 2.4 GHz, with the maximum collector-emitter voltage set to the open-emitter breakdown voltage of 9 V.

(Invited) On the Potential of Lateral BJTs and SiGe HBTs in Advanced CMOS Technologies

The potential of lateral bipolar transistors, based on Horizontal Current Bipolar Transistor (HCBT), in scaled CMOS technologies are examined by TCAD simulations. Thorough and consistent simulations show that SiGe HCBT can achieve fT /fmax of 358/490 GHz outperforming standard vertical-current HBT with fT /fmax of 348/423 GHz, assuming the same intrinsic transistor doping profile. By optimizing the extrinsic base shape and width, the characteristics of SiGe HCBT can be further improved. SiGe HCBTs in bulk silicon substrates result in better performance comparing to the transistors in SOI substrates.

Horizontal Current Bipolar Transistor (HCBT) Technology for High Linearity RF Mixers

The high linearity downconversion active mixers are demonstrated in the horizontal current bipolar transistor (HCBT) technology. The HCBTs fabricated by uniform n-collector doping profile, long hydrofluoric (HF) etching, and long tetramethylammonium hydroxide (TMAH) etching are shown to be optimal for mixer performance. The circuits fabricated with the optimum HCBTs in 180-nm bipolar complementary metal-oxide semiconductor (BiCMOS) process are packaged and measured, resulting in the best HCBT mixer characteristics published so far. The HCBT mixer uses a double-balanced Gilbert cell core with an integrated local oscillator (LO) buffer driver and employs an open-collector output topology. It provides broadband operation and frequency downconversion, measured up to 3 GHz, with a maximum power consumption of 550 mW at the peak linearity performance. The measured peak input third-order intercept point (IIP3) and conversion gain (CG) of 30.3 dBm and 6.0 dB, respectively (at 900-MHz input), are suitable for the base station transceivers and wireless infrastructure. The HCBT technology represents a low-cost BiCMOS platform capable of meeting the various requirements in the fabrication of the radio frequency integrated circuits (RFICs).

A High-Voltage Single-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor for BiCMOS Integration

A novel high-voltage single-emitter horizontal current bipolar transistor (HCBT) is presented. Breakdown voltage improvement compared to high-speed transistor is obtainedwith full depletion of the intrinsic collectorby using implanted CMOS p-well region. Transistors with $\text {BV}_{\text {CEO}} = {10.5}$ V and ${f}_{T} = {15.8}$ GHz are demonstrated. Higher operating currents can be easily obtained by stretching the emitter length resulting in a flexible physical design of circuits. The transistor is fabricated in 0.18- $\mu \text{m}$ HCBT BiCMOS process flow without the additional process steps and the use of additional lithography masks.

Corrigendum: Tomislav Suligoj, Marko Koricic, Josip Zilak, Hidenori Mochizuki, So-Ichi Morita, Katsumi Shinomura, Hisaya Imai, Horizontal current bipolar transistor (NCBT) - a low-cost, high-performance flexible BICMOS technology for RF communication applications. Facta universitatis, series: Electronics and Energetics (FU Elec Energ), vol. 28, no 4, december 2015, pp. 507 - 525. DOI: 10.2298/FUEE1504507S

The Editor-in-Chief has been informed that in the article Tomislav Suligoj, Marko Koricic, Josip Zilak, Hidenori Mochizuki, So-Ichi Morita, Katsumi Shinomura, Hisaya Imai. Horizontal Current Bipolar Transistor (HCBT) - A Low-Cost, High-Performance Flexible BICMOS Technology for RF Communication Applications. Facta Universitatis, Series: Electronics and Energetics, Vol. 28. No 4, 2015, pp. 507-525. DOI: 10.2298/FUEE1504507S Fig. 15 with its legend has been ommited in published version of the paper. After further discussion with the corresponding author, Editor-in-Chief has decided to publish a corrigendum for this article, providing the figure and legend of Fig. 15.<br><br><font color="red"><b> Link to the corrected article <u><a href="http://dx.doi.org/10.2298/FUEE1504507S">10.2298/FUEE1504507S</a></b></u>

Reliability Degradation Mechanisms of Horizontal Current Bipolar Transistor

The impact of the reverse-bias emitter-base stress and the mixed-mode stress on horizontal current bipolar transistor (HCBT) reliability characteristics is analyzed. Under the stress conditions, hot carriers are generated and injected toward silicon-oxide interfaces above and below HCBT’s emitter n+ polysilicon region where the traps responsible for the base current and beta ( $\beta $ ) degradations are formed. Different degradation rates of three HCBT structures measured under both stresses suggest various contributions of the top and bottom oxides to total damage. A larger contribution of the top interface under the reverse-bias emitter-base stress and of the bottom interface under the mixed-mode stress is determined. A lower doping concentration in the bottom part of the intrinsic transistor and a shorter emitter polysilicon predeposition oxide etching both reduce the generation of interface traps during stress tests. The time-dependent trap degradation simulations are run on the structures with the realistic doping profiles to explain the measured stress data on various HCBT structures.

Double-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor With 36 V Breakdown Integrated in BiCMOS at Zero Cost

A novel double-emitter horizontal current bipolar transistor (HCBT) with reduced-surface-field (RESURF) region is presented. The structure is integrated with standard 0.18-μm CMOS, together with high-speed HCBT with BVCEO = 3.6 V and double-emitter HCBT with BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> = 12 V. The second RESURF drift region is formed using a standard CMOS p-well implant for the formation of local substrate below the extrinsic collector. Collector-emitter breakdown is completely avoided by the E-field shielding. Breakdown occurs between the collector and the substrate and equals 36 V. The transistor is fabricated in HCBT BiCMOS process flow without the additional process steps and the use of additional lithography masks.

Horizontal current bipolar transistor (HCBT) - a low-cost, high-performance flexible BiCMOS technology for RF communication applications

In an overview of Horizontal Current Bipolar Transistor (HCBT) technology, the state-of-the-art integrated silicon bipolar transistors are described which exhibit f T and f max of 51 GHz and 61 GHz and f T BV CEO product of 173 GHzV that are among the highest-performance implanted-base, silicon bipolar transistors. HBCT is integrated with CMOS in a considerably lower-cost fabrication sequence as compared to standard vertical-current bipolar transistors with only 2 or 3 additional masks and fewer process steps. Due to its specific structure, the charge sharing effect can be employed to increase BV CEO without sacrificing f T and f max . Moreover, the electric field can be engineered just by manipulating the lithography masks achieving the high-voltage HCBTs with breakdowns up to 36 V integrated in the same process flow with high-speed devices, i.e. at zero additional costs. Double-balanced active mixer circuit is designed and fabricated in HCBT technology. The maximum IIP3 of 17.7 dBm at mixer current of 9.2 mA and conversion gain of -5 dB are achieved. This article has been corrected. Link to the correction DOI:10.2298/FUEE1703429E

Double-Emitter HCBT Structure—A High-Voltage Bipolar Transistor for BiCMOS Integration

Fabrication of a novel high-voltage double-emitter horizontal current bipolar transistor (HCBT) structure integrated with the standard 0.18-μm CMOS and high-speed HCBT is presented. The device takes advantage of 3-D collector charge sharing to achieve full depletion of the intrinsic collector region and to limit the electric field at the base-collector junction. Transistors with BVCEO = 12.6 V, fT ·BVCEO = 160 GHz·V , and β·VA = 28 700 V are demonstrated. The device is fabricated in HCBT BiCMOS process flow without the use of additional lithography masks and represents a zero-cost solution for integration of a high-voltage bipolar device.

Design considerations for integration of Horizontal Current Bipolar Transistor (HCBT) with 0.18 μm bulk CMOS technology

Design issues associated with integration of Horizontal Current Bipolar Transistor (HCBT) with 0.18 μm bulk CMOS process are examined and the effects of fabrication parameters on transistor performance analyzed. HCBT is fabricated on a sidewall of a silicon hill defined by shallow trench isolation (STI). Height of the transistor is limited by the STI depth of 350 nm. Impact of vertical and horizontal dimensions on electrical performance of the transistor are analyzed by simulations with emphasis on extrinsic base design. Base current is reduced by high extrinsic base concentration and increased link-base length. Current gain is increased from 16 to 67 for transistor processed with the optimized extrinsic base profile. High-frequency performance is degraded by the collector charge sharing effect and can be improved by the larger separation between the extrinsic base and emitter, which is achieved with a small thickness of emitter polysilicon region. Misalignment tolerances of the extrinsic base implantation mask show no great impact on transistor’s AC performance.

Horizontal Current Bipolar Transistor With a Single Polysilicon Region for Improved High-Frequency Performance of BiCMOS ICs

A new horizontal current bipolar transistor (HCBT) with a single polysilicon region and a CMOS gate polysilicon near the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> emitter region is integrated with CMOS technology with the addition of two or three masks (three or four masking steps) and a small number of additional fabrication steps. The single-poly HCBT with an optimized collector exhibits f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 51 and 61 GHz, respectively, and an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> product of 173 GHz · V, which are the best reported HCBT characteristics to date and among the highest performance Si BJTs. An HCBT with only two additional masks to CMOS has f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 43 and 53 GHz, respectively, and an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> SV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> product of 120 GHz · V. The developed innovative fabrication techniques enable a very low-cost BiCMOS platform for wireless communication circuits.

Horizontal Current Bipolar Transistor (HCBT) Process Variations for Future RF BiCMOS Applications

Two different process designs of horizontal current bipolar transistor (HCBT) technology suitable for future RF BiCMOS circuits are presented. The active transistor region is built in the defect-free sidewall of 900-nm-wide n-hills on a [110] wafer. The collector n-hill region is partially etched at the extrinsic base-collector periphery, whereas the extrinsic base is self-protected, resulting in reduced collector-base capacitance (C/sub BC/) and minimized volume of the extrinsic regions. The effect of doping levels at different regions on the transistor performance is examined in the two process designs. The fabricated HCBTs exhibit cutoff frequencies (f/sub T/) from 19.2 to 25.6 GHz, maximum frequencies of oscillations (f/sub max/) from 32.2 to 39.6 GHz, and collector-emitter breakdown voltages (BV/sub CEO/) between 4 and 5.2 V, which are the highest f/sub T/ and the highest f/sub T//spl middot/BV/sub CEO/ product compared to existing silicon-on-insulator (SOI) lateral bipolar transistors (LBTs). The compact nature of the HCBT structure and low-cost technology make it suitable for integration with advanced pillar-like CMOS and SOI CMOS devices.

A new HCBT with a partially etched collector

A novel horizontal current bipolar transistor (HCBT), suitable for the integration with the pillar-like MOSFETs, is processed with the reduced volume of the parasitic regions, achieved by the partial etching of the collector n-hill region and the self-protection of the p/sup +/ extrinsic base from tetramethyl ammonium hydroxide etch-back. The HCBT fabricated by a low-cost technology exhibits the cutoff frequency (f/sub T/) of 30.4 GHz, the maximum frequency of oscillations (f/sub max/) of 35GHz and the collector-emitter breakdown voltage (BV/sub CEO/) of 4.2 V, which are the highest f/sub T/ and the highest f/sub T/BV/sub CEO/ product among the lateral bipolar transistors (LBTs).

A low-cost horizontal current bipolar transistor (HCBT) technology for the BiCMOS integration with FinFETs

A novel Horizontal Current Bipolar Transistor (HCBT) is processed with the scaled down dimensions and the improved technology. The active transistor region is built in the defect-free sidewall of the 580 nm wide n-hills in the (1 1 0) wafer, implying the reduction of the parasitic region's volume, i.e. the extrinsic base and the collector. The fabricated HCBT exhibits the cutoff frequency ( f T) of 21.4 GHz, the maximum frequency of oscillations ( f max) of 32.6 GHz and the collector–emitter breakdown voltage (BV CEO) of 5.6 V, which are the highest f T and the highest f TBV CEO product among the lateral bipolar transistors (LBTs).

Fabrication of horizontal current bipolar transistor (HCBT)

The fabrication and characterization of very compact horizontal current bipolar transistor (HCBT) is presented. The active transistor region is processed in the sidewalls of the n-hill, which makes this structure attractive for the integration with pillar-like CMOS with minimum process additions. HCBT technology is simple with 5 lithography masks. The active n-hills are isolated by newly developed chemical-mechanical planarization (CMP) and etch back of oxide. The <110> substrate is used for HCBT fabrication utilizing <111> crystal planes as the active sidewalls. This enables the use of crystallographic dependent etchants for the minimization of the sidewall roughness and dry etching defects, as well as increases the controllability and repeatability of intrinsic transistor doping process. The active transistor regions are processed by angled ion implantation in self-aligned manner. The processed structures result in a cutoff frequency-breakdown voltage (f/sub T/BV/sub CEO/) product of 69.5 GHzV and current gain-Early voltage (/spl beta/V/sub A/) of 4800 V. The high-frequency characteristics are limited by the wide extrinsic base due to the coarse lithography resolution used for fabrication. It is shown by simulations that the improvement of (f/sub T/) and maximum oscillation frequency (f/sub max/) up to 24 and 50 GHz, respectively, can be achieved with finer lithography employed.

Horizontal current bipolar transistor (HCBT): a new concept of silicon bipolar transistor technology

A new concept of silicon bipolar transistor technology is proposed. The resulting horizontal current bipolar transistor (HCBT) is simulated assuming the 0.25 /spl mu/m technology. The surface of the device is smaller than conventional super-self aligned bipolar transistors. The same doping profile as in known vertical current devices is achieved by simpler technology using single polysilicon layer, without conventional epitaxial and n/sup +/ buried layers and with reduced number of lithography masks and technological steps. The simulated dc and ac characteristics of HCBT are similar to the characteristics of standard SST devices.