(Invited) On the Potential of Lateral BJTs and SiGe HBTs in Advanced CMOS Technologies

Abstract

State-of-the-art SiGe HBTs have achieved astonishing performance demonstrating record fT /fmax of 505/720 GHz in bipolar-only process [1] and fT /fmax in the 300-400 GHz range in the commercial BiCMOS technologies [2-4], making them suitable for RF and millimeter wave applications as well as for high-performance analog and mixed-signal circuits. A number of fabrication steps must be added to CMOS backbone technology to obtain such high-performance self-aligned SiGe HBTs that generally include at least two polysilicon layers, one or more epitaxial growths, deep trenches, multiple spacers and other isolation and/or sacrificial layers. Although SiGe HBTs can be implemented several technology nodes behind CMOS with competitive or better RF performance, the addition of those fabrication steps and lithography masks notably increases the cost of technology. Furthermore, high-breakdown voltage HBTs are beneficial for higher-swing applications, such as RF power amplifiers, and their fabrication with high-speed transistors in the same process usually requires various collector implantation schemes, increasing the number of added masks and steps further. Lateral bipolar transistors (LBTs) could principally provide a viable solution for a tradeoff between technological complexity and high-performance due their compact structure where intrinsic transistor regions are more easily accessible from the silicon surface. However, their electrical characteristics in pure-silicon are inferior to those of standard vertical-current transistors so far [5, 6]. As the most advanced lateral-current-flow device, Horizontal Current Bipolar Transistor (HCBT) (Fig. 1.a) [7] has optimum doping profile with low parasitics and is the highest-speed implanted-base Si BJTs, integrated with CMOS in low-cost technology and with the capability to adjust breakdown voltage without any increase in process complexity [8], just by layout manipulation. Due to lateral current flow, the electric field from collector can be shielded in various ways: by recessed CMOS p-well region (Fig. 1.b) increasing BV CEO above 10 V; by double emitter structure with BV CEO>12 V (Fig. 1.c); by double emitter structure with recessed p-well with BV CEO>36 V (Fig. 1.d); and by floating field plates with BV CEO>45 V (Fig. 1.e). Such a wide range of breakdown voltages in the same technology enables: (i) the implementation of high-voltage circuits currently covered by Bipolar-CMOS-DMOS (BCD) process in HCBT technology, (ii) integration of such high-voltage, i.e. power-management and/or analog circuits with RF circuits.The potential of HCBT concept with SiGe base is examined by TCAD simulations. SiGe base stack is placed on the sidewall of the active collector region, as shown in Fig. 2, instead of implanted intrinsic base. The extrinsic base p+ region is implanted into the top part of the grown stack. The electrical characteristics are consistently compared to the self-aligned vertical-current SiGe HBT with the geometry corresponding to the most advanced devices from literature (Fig. 3). Both structures have the same intrinsic doping profile, shown in Fig. 4. Since the extrinsic base overhangs the active collector region in HCBT introducing extrinsic C BC and affecting the collector current distribution, its doping profile shape critically impacts the high-frequency performance. The fT and fmax of the HCBT structure in Fig. 2 are similar to those of vertical current HBT with f T lower by 11 GHz and f max basically equal, whereas the HCBT with more realistic extrinsic base shape results in the improved fT /fmax up to 358/490 GHz (Fig. 5), without impacting β and BV CEO, as shown in Table I. Due to the one-sided base contact, HCBT has higher RB and lower CBC per emitter length and for a given IC HCBT has to be twice longer resulting in a smaller RB and a bit higher CBC than in vertical-current HBT. The interface resistance between the base polysilicon and intrinsic base in vertical-current HBTs is not accounted for in simulations, but has been identified as significant contributor to total RB [1,3]. This RB component is eliminated in SiGe HCBT since the extrinsic base is directly metal-contacted without p+ polysilicon, implying a further improvement of RB in favor of HCBT in actual devices. The fT /fmax can be increased by reducing wbext as can be expected in down-scaling, as shown in Fig. 6, reaching fT /fmax of 375/505 GHz for wbext =45 nm and converging to an ideal 1D transistor. Applying the same concept to SOI substrate, fT /fmax are decreased (Fig. 7) due to denser current distribution in collector boosting the Kirk effect and increasing RC .Simulation study clearly show that HCBT concept can provide state-of-the-art high-frequency performance with vertical-current HBTs as a reference, while implemented in lower-cost technology with simpler integration schemes, that include high-voltage transistors, with both bulk and SOI advanced CMOS. Figure 1