Reliability Degradation Mechanisms of Horizontal Current Bipolar Transistor

Abstract

The impact of the reverse-bias emitter-base stress and the mixed-mode stress on horizontal current bipolar transistor (HCBT) reliability characteristics is analyzed. Under the stress conditions, hot carriers are generated and injected toward silicon-oxide interfaces above and below HCBT’s emitter n+ polysilicon region where the traps responsible for the base current and beta ( $\beta $ ) degradations are formed. Different degradation rates of three HCBT structures measured under both stresses suggest various contributions of the top and bottom oxides to total damage. A larger contribution of the top interface under the reverse-bias emitter-base stress and of the bottom interface under the mixed-mode stress is determined. A lower doping concentration in the bottom part of the intrinsic transistor and a shorter emitter polysilicon predeposition oxide etching both reduce the generation of interface traps during stress tests. The time-dependent trap degradation simulations are run on the structures with the realistic doping profiles to explain the measured stress data on various HCBT structures.