Higher Read Static Noise Margin Research Articles

Robust transmission gate-based 10T subthreshold SRAM for internet-of-things applications

This paper presents a transmission-gate-based 10T (TG10T) subthreshold SRAM cell for internet of things applications. To estimate its relative strength, it is compared with six-transistor (6T), transmission gate (TG)-based 8T (TG8T), and fully differential 8T (FD8T) cells subjected to severe process variations. The simulation results are carried out using HSPICE software and a 16 nm CMOS technology node. The TG10T cell uses a differential scheme to enhance the sense margin, two TGs instead of two NMOS access transistors to enhance write-ability, and two extra buffer transistors to improve read stability. The proposed TG10T cell minimizes leakage power dissipation by means of a greater number of PMOS devices. The proposed cell shows at least a 1.67X lower read delay (T RA) and a 1.13X higher read static noise margin. In addition, it offers a 1.22X and 1.52X lower write delay (T WA), and a 1.36X and 1.40X higher write static noise margin (WSNM) than that of 6T and FD8T, respectively. The TG10T cell consumes 2.06X/1.28X lower dynamic/leakage power compared to the 6T cell. For all these improvements, it incurs a penalty of 1.24X T WA, 1.48X WSNM, and 1.12Xdynamic power when compared with the TG8T cell, at V DD = 0.36 V. However, when subjected to severe process variations, the proposed TG10T cell shows high reliability. Moreover, a 2 kb SRAM memory using the proposed TG10T cell along with peripheral circuitries is implemented to evaluate the proposed cell’s performance in an array level.

A highly reliable radiation tolerant 13T SRAM cell for deep space applications

This paper proposes a highly reliable radiation-tolerant 13T (HRRT 13T) SRAM cell for deep-space applications. The proposed SRAM cell design can effectively tolerate radiation events. The design metrics of the proposed SRAM cell are compared with conventionally used SRAM cells like QUCCE 10T, QUCCE 12T and standard 6T SRAM cells. The proposed SRAM cell consumes 9.4% and 14% lesser hold power (HPWR) compared to QUCCE 10T and QUCCE 12T SRAM cells, respectively. The proposed SRAM cell exhibits 12.7%, 3.63% and 11.7% shorter read access time (TRA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at a nominal supply voltage (VDD) of 0.7 V. The proposed HRRT 13T SRAM cell exhibits higher read stability compared to other conventionally used SRAM cells. This has been validated by 2.92×, 2.33× and 2.06× higher read static noise margin (RSNM) exhibited by the proposed cell compared to the 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed SRAM cell exhibits high radiation tolerance capability compared to the conventionally used SRAM cells. This has been proved by 94.1%, 17.8% and 10.0% higher critical charge (QC) of the proposed cell compared to 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed cell achieves all these improvements at the expense of 1.05×, 1.38× and 1.36× longer write delay (TWA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at VDD = 0.7 V. Extensive simulations on SPICE using 16-nm CMOS technology are performed to validate the theoretical design of the proposed SRAM cell.

Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption

Tunnel field-effect transistors (TFETs) have become a potential candidate for replacing traditional MOSFETs in ultralow-power applications, in future. However, the forward p-i-n current of the TFET can seriously deteriorate the performance of the static random-access memory (SRAM) circuit. This brief proposes a half-select disturb-free 10T TFET SRAM cell with cascode isolation transistors. The proposed 10T SRAM cell can avoid the forward p-i-n current, drastically decreasing its leakage power consumption. At a supply voltage of 0.6 V, the leakage power consumption of the proposed 10T TFET SRAM cell is approximately four orders of magnitude lower than those of the outward-facing access transistor 6T (O_6T)/7T and the Schmitt–Trigger 10T (ST_10T) SRAM cells; the write power consumption is approximately 97% and 98% lower than those of the O_6T/7T/ST_10T and the combinational access 10T (CA_10T) SRAM cells, respectively. Moreover, the 10T SRAM cell exhibits 20% and 57% higher read static noise margin(RSNM) than those of the O_6T/7T and ST_10T cells, 115% and 411% higher write static noise margin(WSNM) than those of O_6T/7T and CA_10T, respectively, 20% higher hold static noise(HSNM) than those of O_6T/7T/ST_10T cells, and 89.8% lesser write delay than that of CA_10T at VDD = 0.6V, indicating that the proposed 10T SRAM cell has great potential for ultra-low power applications.

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

SummaryThis paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

Design of multi-cell upset immune single-end SRAM for low power applications

The on-chip static random access memory (SRAM) has been under revamp due to swift growth in demand of power-efficient internet-of-things based devices. In this context, a low power transmission gate based read decoupled 9-transistor (TRD9T) SRAM bit-cell has been proposed in this work. The proposed cell efficiently minimizes the power dissipation in terms of static/dynamic power and maintains the stability during read, write and standby mode as compared to five recent reported designs. The proposed cell is less vulnerable to soft errors due to improved critical charge that is followed elimination of half-select issue that facilitates bit-interleaved implementation. In addition to conventional 6T (Conv.6T) SRAM, it has been compared with five already reported designs such as tunable-access 8T (TU8T), single ended disturb free 9T (SEDF9T), P-P-N based 10T (P10T), low power 10T (LP10T) and data dependent 11T (D11T) bit-cells, for evaluating the relative performance of proposed design in terms of key design metrics. The reduction in soft error in proposed design is indicated by 1.14×/1.07×/0.99×/1.39×/1.05× improvement in critical charge in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T respectively. The proposed cell mitigates half-select issue to achieve the capability of implementing bit-interleaved architecture. Moreover, standby power of proposed design is reduced by 2.01×/2.46×/1.58×/0.79×/1.89×/1.90× in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T respectively and this improvement sustains at temperature variation from at 27 °C to 110 °C. The TRD9T exhibits 1.97×/1.87×/1.01×/1×/1.01×/1.78× higher read static noise margin and 1.17×/1.21×/1.44×/1.44×/1.11×/0.85× higher write static noise margin in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T respectively. Also, 1.70×/1.29×/2.09×/1.49×/1×/1.60× and 1.48×/1.77×/2.75×/1.77×/1.64×/2.28× improvement in read power and write power respectively is achieved in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T. The read access time of proposed design is improved by 1.31×/1.01×/2.12×/1.18×/1.01×/1.13× in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T. Proposed TRD9T show narrower variability in read stability, read power and read current in comparison to conv. 6T. The proposed TRD9T also exhibits best Electrical quality metric (EQM) among the cells considered in this work.

A Schmitt-trigger based low read power 12T SRAM cell

In this article, a Schmitt trigger based 12-Transistors(ST12T) static random-access memory (SRAM) bit-cell has been proposed. The Read Power of proposed cell is reduced by 29.17%/ 24.14% /7.66% /5.87% /7.67% /16.62% when compared to 6T/ 7T/ TA8T/ 9T/ PPN10T/ D2p11T SRAM cells. Proposed ST12T cell also shows 1.52 $$\times$$ and 1.86 $$\times$$ lesser variability in read current and read power respectively as compared to conventional 6T SRAM cell. Further, the write access time/read access time of the proposed topology are improved by $$1.71 \times /1.82 \times$$ as compared to 6T SRAM cell. The read power delay product of proposed ST12T cell is minimum with variation in supply voltage from 0.5 to 1 V when compared with all considered SRAM cells. ST12T SRAM cell also exhibits 26.82% and 8.87% higher read static noise margin and write static noise margin respectively as compared to conventional 6T SRAM cell. This may be attributed to Schmitt trigger design of inverters in core latch of proposed SRAM cell. The proposed bit-cell is free from half select issue and supports bit interleaving format. Authors have used cadence virtuoso tool with Generic Process Design Kit 45 nm technology file to carry out simulation.

Characterization of single-ended 9T SRAM cell

We present a circuit-level technique of designing a lower write-power along with variability-resistant 9-MOFTET static random-access memory cell. Our proposed bitcell exhibits lower write-power consumption owing to reduction of activity factor and breakup of feedback path between the cross-coupled inverters during write operation. It exhibits higher read static noise margin (by 3.09 ×) compared with standard 6T SRAM cell @ minimum-area. LP9T shows higher static margin for write operation (by 41%) compared with 8T (S6T) @ iso-area (minimum-area). These improvements are achieved due to breakup of feedback path during the process of writing a bit on to the storage node. The paper investigates in detail the influence of variation in process related parameters, environmental parameters such as supply voltage and temperature on most of the important design parameters of the bitcell and compares the obtained simulation results with conventional 6-MOSFET (6T) and 8-MOSFET (8T) bitcells. It demonstrates its invariableness by showing 1.5 × tighter disperse in read time variability with a cost of 1.41 × higher read time compared with S6T @ minimum-area. It also exhibits 39% narrower disperse in read time variability in comparison to 8T @ iso-area. It draws lower power (2.06 ×) from supply voltage while flipping of stored data during write mode compared with standard 8T SRAM cell @ iso-area. It also compares key design metrics of LP9T with those of few other 9T SRAM cells found in the literature. This work also realizes the proposed design using CNFET. The CNFET-based design outperforms its CMOS counterpart in all respect.

Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology

PurposeThis paper aims to propose a new ten-transistor (10T) SRAM bit-cell with differential read and write operations. The cell structure has read buffer on each side of the cell to improve read performance and comprises six main body transistors’ connections similar to the commercial 6T SRAM cell to improve write performance. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on a silicon-on-insulator (SOI) substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher read static noise margin (RSNM) as compared with that of 8T and 6T bit-cells, respectively, at a VDD of 0.9 V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit- cell. The overall electrical quality of the SRAM circuit with the proposed bit-cell is enhanced up to 1.673 times and 1.22 times as compared with the 8T SRAM-NEW and 6T bit-cells, respectively.Design/methodology/approachA new 10T SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on an SOI substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell.FindingsThe proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher RSNM as compared with that of the 8T and 6T bit-cells, respectively, at a VDD of 0.9V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with the 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit-cell.Originality/valueThe proposed bit-cell is novel compared with existing bit-cells.

Correlated Material Enhanced SRAMs With Robust Low Power Operation

We propose a novel static random access memory (SRAM) cell employing correlated material (CM) films in conjunction with the transistors to achieve higher read stability, write ability, and energy efficiency. The design of the proposed SRAM cell utilizes orders of magnitude difference in the resistance of the insulating and metallic phases of the CM to mitigate the design conflicts. By appropriately controlling the phase transitions in the CM films during SRAM operation through device–circuit codesign, we achieve 30% higher read static noise margin and 36% increase in the write margin over standard SRAM. The proposed design also leads to a 50% reduction in the leakage current due to high insulating state of the CM. This is achieved at 28% read time penalty. We also discuss the layout implications of our technique and present techniques to sustain no area overhead.

A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell

A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single-ended with dynamic feedback control 8T static RAM (SRAM) cell enhances the static noise margin (SNM) for ultralow power supply. It achieves write SNM of $1.4\times $ and $1.28\times $ as that of isoarea 6T and read-decoupled 8T (RD-8T), respectively, at 300 mV. The standard deviation of write SNM for 8T cell is reduced to $0.4\times $ and $0.56\times $ as that for 6T and RD-8T, respectively. It also possesses another striking feature of high read SNM $\sim 2.33\times $ , $1.23\times $ , and $0.89\times $ as that of 5T, 6T, and RD-8T, respectively. The cell has hold SNM of $1.43\times $ , $1.23\times $ , and $1.05\times $ as that of 5T, 6T, and RD-8T, respectively. The write time is 71% lesser than that of single-ended asymmetrical 8T cell. The proposed 8T consumes less write power $0.72\times $ , $0.6\times $ , and $0.85\times $ as that of 5T, 6T, and isoarea RD-8T, respectively. The read power is $0.49\times $ of 5T, $0.48\times $ of 6T, and $0.64\times $ of RD-8T. The power/energy consumption of 1-kb 8T SRAM array during read and write operations is $0.43\times $ and $0.34\times $ , respectively, of 1-kb 6T array. These features enable ultralow power applications of 8T.

Novel 8T Bit-cell with High RSNM for Sub-threshold SRAM

Since the sub-threshold circuit technology was widely applied to SRAM circuit, the power supply voltage was greatly reduced, and then, the performance of environmental parameters and process deviations on sub-threshold circuit become critical. The changes in environmental parameters and process deviations easily make traditional 6T SRAM circuit lead to fatal errors, particularly, the Read Static Noise Margin (RSNM) is deteriorated obviously. In order to improve the performance of RSNM, we proposed a novel 8T SRAM bit-cell which uses the read and write separation structure and Partial Dynamic Threshold voltage (PDT) technology. This paper firstly introduces the PDT technology and read and write separation structure; then proposes the novel 8T structure and explains the operating principle of the 8T bit-cell; finally gives the result of the simulation for the stability performance of the 8T bit-cell compare to other 3 kinds of 6T bit-cell. The comparison results show that the proposed 8T bit-cell greatly improves the RSNM of the SRAM bit-cell.

Super-Fast Low Power (SFLP) SRAM Cell for Read/Write Operation

In this paper a Super-Fast Low-Power (SFLP) static random access memory (SRAM) cell has been proposed. The SFLP cell contains two tail transistors in the pull-down path of the respective inverter to minimize the write power consumption The cell is simulated in terms of speed, power and read stability. The simulated results show that the read and write power of the proposed cell is reduced up to 38% and 55% at 1.2 V respectively and cell achieves 2.2x higher read static noise margin (SNM) compared to the conventional 6T SRAM cell.

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read-stability as well as better write-ability compared to the standard 6T bitcell. The proposed ST bitcells incorporate a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes. A detailed comparison of different bitcells under iso-area condition shows that the ST-2 bitcell can operate at lower supply voltages. Measurement results on ten test-chips fabricated in 130-nm CMOS technology show that the proposed ST-2 bitcell gives 1.6× higher read static noise margin, 2× higher write-trip-point and 120-mV lower read-Vmin compared to the iso-area 6T bitcell.

A Robust High Density 7T Subthreshold SRAM Bitcell with Partial Dynamic Threshold Voltage Connection Scheme

Combined with partial dynamic threshold MOSFET connection scheme, a high density 7T subthreshold SRAM bitcell operating at supply voltage of 200 mV is proposed in this paper. Dual write and single read ensures high read static noise margin of the SRAM bitcell without expense of writability degradation. The 7T SRAM exhibits robust efficiency, making the design less vulnerable to process variation. Compared to the referenced 6T and the 8T SRAM bitcell, the proposed bitcell has four aspects of improvement: (1) 5.1% and 6.1% larger hold margin, (2) 80.6% and 85.5% of standard deviation, (3) 50% and 18% reduction of area (at 200 mV), and (4) 16X and 32X bitcells per bitline. To our best knowledge, the area penalty of proposed SRAM is the smallest with robustness and functionality of subthreshold SRAM achieved.

A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM

We propose a novel Schmitt trigger (ST) based differential 10-transistor SRAM (static random access memory) bitcell suitable for subthreshold operation. The proposed Schmitt trigger based bitcell achieves 1.56 x higher read static noise margin (SNM) ( Vdd = 400 mV) compared to the conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built-in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes differential operation and hence does not require any architectural changes from the present 6T architecture. At iso-area and iso-read-failure probability the proposed memory bitcell operates at a lower (175 mV) Vdd with 18% reduction in leakage and 50% reduction in read/write power compared to the conventional 6T cell. Simulation results show that the proposed memory bitcell retains data at a supply voltage of 150 mV. Functional SRAM with the proposed memory bitcell is demonstrated at 160 mV in 0.13 mum CMOS technology.