Robust transmission gate-based 10T subthreshold SRAM for internet-of-things applications

Abstract

This paper presents a transmission-gate-based 10T (TG10T) subthreshold SRAM cell for internet of things applications. To estimate its relative strength, it is compared with six-transistor (6T), transmission gate (TG)-based 8T (TG8T), and fully differential 8T (FD8T) cells subjected to severe process variations. The simulation results are carried out using HSPICE software and a 16 nm CMOS technology node. The TG10T cell uses a differential scheme to enhance the sense margin, two TGs instead of two NMOS access transistors to enhance write-ability, and two extra buffer transistors to improve read stability. The proposed TG10T cell minimizes leakage power dissipation by means of a greater number of PMOS devices. The proposed cell shows at least a 1.67X lower read delay (T RA) and a 1.13X higher read static noise margin. In addition, it offers a 1.22X and 1.52X lower write delay (T WA), and a 1.36X and 1.40X higher write static noise margin (WSNM) than that of 6T and FD8T, respectively. The TG10T cell consumes 2.06X/1.28X lower dynamic/leakage power compared to the 6T cell. For all these improvements, it incurs a penalty of 1.24X T WA, 1.48X WSNM, and 1.12Xdynamic power when compared with the TG8T cell, at V DD = 0.36 V. However, when subjected to severe process variations, the proposed TG10T cell shows high reliability. Moreover, a 2 kb SRAM memory using the proposed TG10T cell along with peripheral circuitries is implemented to evaluate the proposed cell’s performance in an array level.