Abstract
In this paper a Super-Fast Low-Power (SFLP) static random access memory (SRAM) cell has been proposed. The SFLP cell contains two tail transistors in the pull-down path of the respective inverter to minimize the write power consumption The cell is simulated in terms of speed, power and read stability. The simulated results show that the read and write power of the proposed cell is reduced up to 38% and 55% at 1.2 V respectively and cell achieves 2.2x higher read static noise margin (SNM) compared to the conventional 6T SRAM cell.
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