Design of multi-cell upset immune single-end SRAM for low power applications

Abstract

The on-chip static random access memory (SRAM) has been under revamp due to swift growth in demand of power-efficient internet-of-things based devices. In this context, a low power transmission gate based read decoupled 9-transistor (TRD9T) SRAM bit-cell has been proposed in this work. The proposed cell efficiently minimizes the power dissipation in terms of static/dynamic power and maintains the stability during read, write and standby mode as compared to five recent reported designs. The proposed cell is less vulnerable to soft errors due to improved critical charge that is followed elimination of half-select issue that facilitates bit-interleaved implementation. In addition to conventional 6T (Conv.6T) SRAM, it has been compared with five already reported designs such as tunable-access 8T (TU8T), single ended disturb free 9T (SEDF9T), P-P-N based 10T (P10T), low power 10T (LP10T) and data dependent 11T (D11T) bit-cells, for evaluating the relative performance of proposed design in terms of key design metrics. The reduction in soft error in proposed design is indicated by 1.14×/1.07×/0.99×/1.39×/1.05× improvement in critical charge in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T respectively. The proposed cell mitigates half-select issue to achieve the capability of implementing bit-interleaved architecture. Moreover, standby power of proposed design is reduced by 2.01×/2.46×/1.58×/0.79×/1.89×/1.90× in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T respectively and this improvement sustains at temperature variation from at 27 °C to 110 °C. The TRD9T exhibits 1.97×/1.87×/1.01×/1×/1.01×/1.78× higher read static noise margin and 1.17×/1.21×/1.44×/1.44×/1.11×/0.85× higher write static noise margin in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T respectively. Also, 1.70×/1.29×/2.09×/1.49×/1×/1.60× and 1.48×/1.77×/2.75×/1.77×/1.64×/2.28× improvement in read power and write power respectively is achieved in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T. The read access time of proposed design is improved by 1.31×/1.01×/2.12×/1.18×/1.01×/1.13× in comparison to conv.6T/TU8T/SEDF9T/P10T/LP10T/D11T. Proposed TRD9T show narrower variability in read stability, read power and read current in comparison to conv. 6T. The proposed TRD9T also exhibits best Electrical quality metric (EQM) among the cells considered in this work.