High-voltage Thin-film Transistors Research Articles

High-performance InGaZnO power transistors: Effect of device structural parameters

In this work, the effect of offset channel length (Loffset) and the dielectric layer thickness (d) on the InSnO/InGaZnO (ITO/IGZO) dual-active-layer (DAL) high-voltage thin-film transistors (HV-TFTs) is systematically investigated. The characteristics of the DAL HV-TFTs resemble that of GaN high electron mobility transistors, wherein the breakdown voltages (VBD) reach saturation at a certain Loffset, and the on-resistance (Ron) linearly increases with Loffset. The linear fitting of Ron vs Loffset indicates that d has a multifaceted impact on the performance of HV-TFTs. In addition to its theoretical role in transistor models, d also influences the channel doping concentration and sidewall deposition issues in practical devices. The DAL HV-TFT with a 30-nm Al2O3 gate dielectric achieves a remarkable VBD of 450 V, the highest figure of merit of 118.2 kW/cm2, and a positive threshold voltage of 3.65 V. Both experiments and simulations indicate that the breakdown occurs within the semiconductor channel, paving the way for further improvement of the performance.

Characteristics of Offset Corbino Thin Film Transistor: A Physical Model

Offset Corbino thin film transistor is a good candidate for high voltage thin film transistor (HVTFT) due to the uniform drain electric field distribution benefiting from the circular structure. The physical model of offset Corbino thin film transistor characteristics has yet to be clarified. In this study, Equations are derived to describe the current–voltage relations of Corbino TFT with offset at the drain or source sides. The influence of offset position and parameters on the saturation voltage and the saturation current was described quantitatively. Three-dimensional Computer-Aided Design simulation and experiment results verify the theoretical physical model. Our physical model provides design rules for high voltage offset Corbino TFT when considering the voltage tolerance and saturation current balance.

P‐1.8: A 3‐Probe Approach to Study Dynamic Operation in High Voltage Thin Film Transistors

P‐1.8: A 3‐Probe Approach to Study Dynamic Operation in High Voltage Thin Film Transistors

Dual-active-layer InGaZnO high-voltage thin-film transistors

InGaZnO high-voltage thin-film transistors (HV-TFTs) with vertical dual-active-layer structure and lateral offset design were fabricated at low temperature. The TFT features such as sub-threshold swing, threshold voltage, and hysteresis voltage are similar to those of the normal devices; furthermore, they are independent of the offset length. The blocking voltage of HV-TFTs with an offset of 10 μm is 406 ± 17 V while the ON/OFF ratio reaches 109 at .

MgZnO Thin Film Transistors on Glass With Blocking Voltage of 900 V

High voltage thin film transistor (HVTFT) built on glass can be used for distributed micro-inverters in the emerging applications, such as the building-integrated photovoltaics (BIPV) and smart glass. We report an HVTFT with a center-symmetric circular configuration which is built on a glass substrate at low temperature. The device is composed of a magnesium zinc oxide (MZO) based channel and a high- $\kappa $ stacked gate dielectric layer of aluminum oxide/silicon dioxide (Al2O3/SiO2). This MZO HVTFT enables a blocking voltage of 900 volts. The high blocking capability is attributed to the lower gate leakage current through the stacked dielectric layer. The device under 10V drain bias shows an on/off current ratio over 109.

Kilo-Voltage Thin-Film Transistors for Driving Nanowire Field Emitters

High-voltage thin-film transistors (HV-TFTs) based on amorphous InGaZnO (a-IGZO) are demonstrated to work in the range of kilo-voltage (kV). The devices feature a high breakdown voltage of over 1.1 kV, on-current of 10.8 $\mu \text{A}$ , and an on/off current ratio over 105. By integrating kV-TFTs with ZnO nanowires, actively controlled field emitters are obtained that exhibit extremely small current fluctuation in the emission current (2.4 % for 3600s). The operating mechanisms of the HV-TFTs are investigated by in-situ measurement of channel potentials and simple equations are derived to describe the current–voltage relations. This study demonstrates the feasibility of using a-IGZO in HV-TFTs that drive large-area field-emitter arrays and provide general understanding and design rules for HV-TFTs designed to drive nanowire field emitters.

Triboelectric‐TFT Flip‐Flop for Bistable Latching of Dielectric Elastomer Actuators

AbstractA high‐voltage flip‐flop combining two self‐powered soft sensors with a flexible high‐voltage thin film transistor (HVTFT) is reported, and is used to electrically latch dielectric elastomer actuators (DEAs) in zero and high‐strain states. Two touch‐actuated triboelectric generators (TENGs) provide the gate input for the HVTFT that drives a DEA. One TENG is of positive polarity, while the other is of negative polarity, thus generating voltages either higher (100 V) or lower (−6 V) than the HVTFT threshold voltage. Used in a high‐voltage inverter configuration, there are two stable output voltage states, here 650 V (the “reset” state) and 50 V (the “set” state). The DEA is thus latched in one of two states, at 17.5% and 0% strain. The 650 V output is stable in time, while the 50 V state drifts up to 350 V after 10 s. Due to the highly nonlinear strain–voltage curve of the DEA, the drift of the output voltage in the “set” state leads only to a 2% increase of the DEA actuation strain in 10 s. By enabling bistable control of DEAs with TENGs, the TENG‐HVTFT latch paves the way toward soft robots with flexible embedded control circuitry.

Yttrium zinc tin oxide high voltage thin film transistors

We demonstrate that doping the semiconductor zinc tin oxide (ZTO) with yttrium leads to a high-voltage thin film transistor (HVTFT) with enhanced switching performance. Adding 5% yttrium leads to an increase in the on-off ratio from 40 to 1000 at an operating voltage of 500 V and to a drop of the subthreshold swing from 65 to 35 V/dec. The performance is improved because of the reduction of the saturation voltage and because of a decrease in the off-current from several μA for undoped ZTO HVTFTs to 100 nA for Y5%ZTO. The decrease in saturation voltage and off-current can be attributed to a lower trap concentration leading to enhanced space-charge limited current and to a decrease in the background charge carrier concentration. At a 500 V bias voltage, an inverter circuit with a yttrium-doped ZTO HVTFT can control the output voltage between 50 V and 500 V, while the undoped ZTO HVTFT can only control the output voltage between 150 V and 450 V. The improvement in high voltage performance of yttrium-doped ZTO HVTFTs is important for future work related to high voltage thin film transistors made of amorphous oxide semiconductors as it demonstrates that this technology enables HVTFTs with simultaneously high operation voltage, high on-current, and high on-off ratio.

ZnO flexible high voltage thin film transistors for power management in wearable electronics

A ZnO-based flexible high voltage thin film transistor (f-HVTFT) is fabricated on a plastic substrate. The f-HVTFT shows a blocking voltage of 150 V, on-current of 170 μA, and off-current of 0.01 pA at a drain bias of 10 V. The maximum recoverable bending radius of the device reaches 11 mm, and the blocking voltage is larger than 120 V while it is under bending. The unique center-symmetric circular structure of the f-HVTFT is particularly useful to the wearable systems, which enable one to operate under bending from arbitrary directions. The ZnO-based f-HVTFT is a promising candidate to be used for power management of self-powered wearable electronic systems.

Self-aligned photolithography for the fabrication of flexible transparent high-voltage thin film transistors, diodes and inverters

We report the realization of flexible fully-transparent high-voltage (HV) inverters composed with a high-voltage thin film transistor (HVTFT) drive and an on-chip high-voltage thin film diode (HVTFD) load. The overall fabrication temperatures are decreased as low as 75 °C to minimize the built-in strain caused by the large thermal expansion mismatch. High on/off ratio of 1010, rectification ratio of 109 and voltage gain of 8.5 are achieved in the flexible HVTFT, HVTFD and HV inverter, respectively. In addition, the flexible HV devices are fabricated with a novel self-aligned photolithography technology, and the fabrication procedure and working principle are depicted in this letter. This work combines HV electronics with the upsurging flexible transparent electronics, and will initiate interdisciplinary researches between the two fields.

Self-aligned photolithography for the fabrication of fully transparent high-voltage devices

High-voltage devices, working in the range of hundreds of volts, are indispensable elements in the driving or readout circuits for various kinds of displays, integrated microelectromechanical systems and x-ray imaging sensors. However, the device performances are found hardly uniform or repeatable due to the misalignment issue, which are extremely common for offset drain high-voltage devices. To resolve this issue, this article reports a set of self-aligned photolithography technology for the fabrication of high-voltage devices. High-performance fully-transparent high-voltage thin film transistors, diodes and logic inverters are successfully fabricated with this technology. Unlike other self-aligned routes, opaque masks are introduced on the backside of the transparent substrate to facilitate proximity exposure method. The photolithography process is simulated and analyzed with technology computer aided design simulation to explain the working principle of the proximity exposure method. The substrate thickness is found to be vital for the implementation of this technology based on both simulation and experimental results. The electrical performance of high-voltage devices is dependent on the offset length, which can be delicately modulated by changing the exposure dose. The presented self-aligned photolithography technology is proved to be feasible in high-voltage circuits, demonstrating its huge potential in practical industrial applications.

Solution-Processed and Self-Assembled Monolayer-Treated High-Voltage Organic Thin Film Transistors for Flexible MEMS Integration

ABSTRACTWe report a 6,13-Bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) solution-processed high-voltage organic thin film transistor (HVOTFT) with a large breakdown voltage of |VDS| > 450 V, a three-fold increase from previous results. An offset channel architecture and an organosilane-based self-assembled monolayer (SAM) treatment were used to achieve large breakdown voltages. Solution-processed HVOTFTs will enable novel high-voltage and flexible applications. Reliability of the HVOTFT under high-field stress was studied in the context of threshold and onset to conduction voltages.

Offset Drain ZnO Thin-Film Transistors for High-Voltage Operation

High-voltage thin-film transistors (TFTs) are useful building blocks for thin-film circuits. In this letter, we demonstrate ZnO high-voltage TFTs with offset drain. For these devices, the drain-to-source breakdown voltage increases from about 30 to >80 V as the drain offset length is increased from 0 to $\sim 2~\mu \text{m}$ , with little degradation in the ${I}$ – ${V}$ characteristics. The fabrication process is simple and uses a maximum temperature of 200 °C, which allows the high-voltage ZnO TFTs to be readily integrated in thin-film circuits on either glass or polymeric substrates.

Flexible Zinc-Tin Oxide Thin Film Transistors Operating at 1 kV for Integrated Switching of Dielectric Elastomer Actuators Arrays.

Flexible high-voltage thin-film transistors (HVTFTs) operating at more than 1 kV are integrated with compliant dielectric elastomer actuators (DEA) to create a flexible array of 16 independent actuators. To allow for high-voltage operation, the HVTFT implements a zinc-tin oxide channel, a thick dielectric stack, and an offset gate. At a source-drain bias of 1 kV, the HVTFT has a 20 µA on-current at a gate voltage bias of 30 V. Their electrical characteristics enable the switching of DEAs which require drive voltages of over 1 kV, making control of an array simpler in comparison to the use of external high-voltage switching. These HVTFTs are integrated in a flexible haptic display consisting of a 4 × 4 matrix of DEAs and HVTFTs. Using a single 1.4 kV supply, each DEA is independently switched by its associated HVTFT, requiring only a 30 V gate voltage for full DEA deflection. The 4 × 4 display operates well even when bent to a 5 mm radius of curvature. By enabling DEA switching at low voltages, flexible metal-oxide HVTFTs enable complex flexible systems with dozens to hundreds of independent DEAs for applications in haptics, Braille displays, and soft robotics.

MgZnO High Voltage Thin Film Transistors on Glass for Inverters in Building Integrated Photovoltaics.

Building integrated photovoltaics (BIPV) have attracted considerable interests because of its aesthetically attractive appearance and overall low cost. In BIPV, system integration on a glass substrate like windows is essential to cover a large area of a building with low cost. However, the conventional high voltage devices in inverters have to be built on the specially selected single crystal substrates, limiting its application for large area electronic systems, such as the BIPV. We demonstrate a Magnesium Zinc Oxide (MZO) based high voltage thin film transistor (HVTFT) built on a transparent glass substrate. The devices are designed with unique ring-type structures and use modulated Mg doping in the channel - gate dielectric interface, resulting in a blocking voltage of over 600 V. In addition to BIPV, the MZO HVTFT based inverter technology also creates new opportunities for emerging self-powered smart glass.

Novel Gate-All-Around High-Voltage Thin-Film Transistor With T-Shaped Metal Field Plate Design

A novel gate-all-around (GAA) high-voltage thin-film transistor (HVTFT) with the T-shaped metal field plate (MFP) design results in a high breakdown voltage ( $V_{\rm BD})_{_{_{}}}$ of 119.9 V and a low specific ON-resistance ( $R_{\rm SP})$ of 8.4 m $\Omega \cdot ~\mathrm{cm}^{2}$ . This T-shaped MFP GAA HVTFT solves the $V_{{\rm {BD}}}$ – $R_{\rm SP}$ tradeoff problems and exhibits superior gate control performance, which leads to excellent electrical characteristics such as a better ON/OFF ratio of $> 10^{10}$ and a lower subthreshold slope of 154.4 mV/decade than the conventional planar structure.

Direct electrostatic toner marking with poly(3,4-ethylenedioxythiophene)polystyrenesulfonate bilayer devices

Poly(3,4-ethylenedioxythiophene)polystyrenesulfonate (PEDOT:PSS) is the one of the most promising and widely used materials for low cost large area flexible displays, owing to its easy solution processing and micro/nano scale patternability. In this work, hole injection between PEDOT:PSS thin film and molecularly doped polymer layers of arylamine has been studied in a bilayer device configuration. The electrical properties of the bilayer devices have been examined by studying their charge-discharge behavior, current-voltage (I-V), and time-of-flight (TOF) characteristics. The work function of the PEDOT:PSS and arylamine has been estimated by electrochemical measurements. Results show that PEDOT:PSS is an efficient hole injector to arylamine owing to its favorable molecular energetics. The efficiency of hole injection depends on the conductivity of the PEDOT:PSS film and the strength of the electric field across the bilayer device. The interfacial electrical contact behavior between PEDOT and arylamine studied by steady state I-V measurements and TOF measurements suggests that for highly conductive PEDOT:PSS, the discharge of the bilayer device is limited by the hole mobility in the charge transport layer whereas it is injection limited for more resistive PEDOT:PSS films. Printing experiments were performed on a modified xerographic DC12 printer as well as a modified DC8000 development housing. The overall results show that the latent image produced by discharging the bilayer device can be developed electrostatically with toner. More importantly, we found that the PEDOT:PSS bilayer device can be charged, discharged, and developed by just loading it against a negatively biased magnetic toner brush. We suggest coupling this direct toner marking process with an active backplane for digital printing application. The proposed digital printer appears to be very simple and compact as printing can be done without using a charger and the laser ROS system and replacing the photoreceptor with the PEDOT bilayer device that is controlled by an active backplane. The operating bias estimated for the Thin Film Transistors (TFTs) in the backplane is about −200 V. We believe that the bias voltage can be further reduced by using a thinner charge transport layer and by optimizing the toner development process. Although the bias voltage is still high, it is within reach for today's high-voltage TFT technology.

High voltage thin film transistors integrated with MEMS

The integration of high voltage thin film transistors with a released MEMS process onto the same substrate is demonstrated. High voltage transistors capable of 800 V actuation voltage are used to actuate released metal cantilevers and membranes with a low temperature fabrication process (<350 °C) on glass substrates. This demonstration is an important step towards realizing MEMS arrays with integrated addressable drivers for applications which require high voltage, such as electrostatic MEMS devices on low temperature substrates (e.g. glass or flex). High voltage thin film transistors (HVTFT) provide the unique property of easily controlling high voltage (50–800 V) using a standard input voltage range (0–20 V). To our knowledge, this is the first demonstration of integrated HVTFT actuating released MEMS structures.

Low-Temperature Power Device: A New Poly-Si High-Voltage LDMOS With Excimer Laser Crystallization

A new low-temperature polysilicon high-voltage LDMOS (LTPS HVLDMOS) using excimer laser crystallization has been proposed for the first time. However, in order to enhance LTPS HVLDMOS characteristics, there are two starting points: 1) integrate the thin-film technology with the power device, and 2) clarify the requirement of excimer laser treatment for low-temperature power devices. As the result, the on/off current ratio after laser treatment is improved over 106 times than that before laser treatment at L/sub drift/ = 15 μm and V/sub ds/ = 25 V. The LTPS HVLDMOS after laser treatment also demonstrates the better tradeoff between the specific on resistance and breakdown voltage against the previous high-voltage thin-film transistors (HVTFTs) by solid-phase crystallization - such as semi-insulating (SI), metal field-plated, and offset-drain HVTFTs.

Radial confinement in lateral power devices

The aim of this paper is to demonstrate a novel, radial confinement approach to improve the breakdown performance of a lateral power device. The key feature is that the drift region width decreases gradually from the anode to the cathode to achieve charge confinement in the radial direction. As a result, the n− drift region concentration can be increased by a factor of 7 in comparison to a conventional counterpart leading to a lower specific on-state resistance. This technique is applicable to silicon-on-insulator technologies, such as the SOI or SOS, and to high-voltage thin-film transistor technologies on glass. Experimental results from radial diodes fabricated in SOS technology show a blocking capability higher than from those of their conventional counterparts.