High-speed Serial Interface Research Articles

Advances in Traditional Electrical Validation of High-Speed Serial Connections Using Innovative Debugging Methods and Machine Learning Models.

As technology continues to shrink and more heterogeneous blocks are combined into single System on a chip (SOCs), the design of high-performance integrated circuits is getting more and more difficult. In the course of silicon validation, which includes testing (Wafer Testing, Automatic Test Equipment), digital validation (Functional Data route, FSM), analogue bench validation (Electrical, Interoperability), and system validation, a number of challenges that arise from the complicated design are uncovered. The process, methods, and constraints of each domain are unique. Electrical problems that have already passed through earlier stages of design are the primary focus of analogue validation. The analogue signal or mix signal nature of IPs makes it impossible for digital validation or any of the other post-silicon domains to discover electrical flaws on its own. As a result, studies focusing on analogue bench validation have grown in prominence. Recent developments in analogue bench validation, focusing on high-speed serial interface in particular, are highlighted in the proposed study. In addition, this article summarises recent technological developments that provide avenues for further study regarding analogue bench validation.

A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces

We report on the development of a time-domain numerical modeling framework to estimate timing jitter in High-Speed Serial Interfaces (HSSI) including a wide range of effects such as Inter-Symbol Interference (ISI) due to channel dispersion, phase noise of transmitter (TX) and receiver (RX) frequency synthesizers and use of bang-bang phase detector in the Clock and Data Recovery (CDR) loop. Based on the step response of the channel, the numerical model computes the response of the system to a random sequence of bits and provides information in terms of eye diagram, bathtub plot and jitter histogram. Different definitions of jitter are investigated, and for each of them we consider the physical effects that are included, eventually identifying that the most complete definition is based on the time distance between the edges instants defined by the CDR and the crossing points of the sampled signal. We also found that this definition is consistent with the features of the bathtub plot. A channel compliant with the PCIe 4.0 standard is used as test vehicle, including the main equalization strategies. The numerical model is then compared to a simple analytical model for the CDR jitter that can be augmented by including Data-Dependent Jitter (DDJ). An approach to system-level analysis based on proper combination of the above elements is eventually proposed to provide quick although accurate aid to the design of CDRs in HSSIs.

A Novel PWAM Signaling Scheme for High-speed Serial Interface

This paper presents a novel PWAM signaling scheme, which combines a dual-mode pulse amplitude modulation-4 (dual-mode PAM-4) and a pulse width modulation-2 (PWM-2). Its combination is different from that of the conventional PWAM scheme [4]. So, the minimum pulse width of the proposed PWAM scheme is increased. The proposed PWAM scheme can reduce the power consumption of the transceiver by decreasing the number of differential levels (X) compared with the existing 4-bit/symbol PAM-X scheme (i.e., dual-mode PAM-10 [2] and PAM-16 [13]). The proposed PWAM transceiver was designed in a 180 nm CMOS process, and it has a target of 10-Gb/s. The power consumption of the transmitter and receiver is 134 ㎽ and 95 ㎽, respectively. The power efficiency of the transmitter and receiver are 13.4 pJ/bit and 9.5 pJ/bit, respectively.

A Low BER DB-PAM4 Adaptive Equalizer for Large Channel Loss in Wireline Receivers

A high-speed serial interface is the core IP of a high-performance computer, data center and interconnection network; its bandwidth and bit error performance restrict the development of the system. With the evolution of high-speed serial interface line rates from 56 G to 112 G in high-end information systems, their bit errors increase sharply, limiting system performance. In order to solve the high-bit-error problem of the 112 Gb/s high-speed serial interface, this paper proposes a low-error Duo-binary PAM4 (DB-PAM) receive equalization technology. This technology utilizes the Duo-binary (DB) signal in which the channel and the transceiving equalizer work together to realize the low-error reception of the 112 Gb/s signal in the high-attenuation channel. To solve the problem of difficulty in generating high-speed DB-PAM4 signals and the complex adjustment of equalization parameters, this paper proposes a two-step progressive equalization technique. In the first step, the technology transmits not-return-to-zero (NRZ) signals at the transmitter (TX) and generates a Duo-binary (DB) signal path at the receiver using the least mean square error (LMS) algorithm. In the second step, the technology sends a precode-PAM4 (pre-PAM4) signal at TX; at the receiving end, the adaptive equalization algorithm is used to adjust the DSP equalization parameters to generate the optimal equalization parameters of the DB-PAM4 signal. This paper uses Cadence’s AMS simulation platform to verify the receive equalizer of DB-PAM4. Simulation results show: when a 112 Gb/s pre-PAM4 signal passes through the 35 dB@28 GHz channel, the receiver (RX) utilizes the adaptive equalizer to generate a 112 Gb/s DB-PAM4 signal, and the receiver bit error rate (BER) is less than 3e-9.

An Overhead-Reduced Key Coding Technique for High-Speed Serial Interface

This paper describes a packet-based overhead-reduced (OR) key coding technique for a high-speed serial interface. The 8B10B code is a de facto standard coding technique in the application but its bit-overhead is 25%. The proposed key coding technique is to reduce the coding overhead and still provides enough bit transition to facilitate clock and data recovery in the receiver. After a key pattern is generated from a certain data stream, input data are encoded and framed as packets along with the generated key for transmission. The packets are transmitted and then decoded as original data in the receiver. Using the proposed coding scheme, 4-, 6-, and 8-bit key coding systems are designed and compared. When a 6-bit key coding encoder/decoder is tested, a packet is composed of a 6-bit OR key header followed by 30 encoded sub-packets, in which each sub-packet has a 6-bit data. In the 6-bit case, the bit overhead is only 3.33% and the maximum continuous run length is 10 bits. To control the running disparity for the AC coupling interface, a logic for selecting the optimal key is implemented to keep the running disparity as low as possible. The running disparity of the encoded data with 6-bit key code is controlled within +/−12.

A Novel Framework for Testing High-Speed Serial Interfaces in Multiprocessor Based Real-Time Embedded System

Recent years has seen a tremendous increase in processing requirements of present-day embedded system applications. Embedded systems consist of multiple processing elements (PEs) connected to each other using different types of interfaces. Many complicated tasks are accomplished by embedded systems in varied settings, which may introduce errors during inter-processor communication. Testing such systems is tremendously difficult and challenging from testing non-real time systems. A major part of testing real time embedded systems involves ensuring accuracy and timing in synchronous inter-process communication More specifically, the synchronization and inter-processor communication of real-time applications makes testing a challenging task and due to the demand for higher data rate increases, day-by-day, making testing of such systems even more complex. This paper presents a novel frame work that uses multiple instances of simulators with physical high-speed serial interfaces to emulate any real time embedded system communication. The framework presents a testing technique that detects all faults related to synchronization of high-speed synchronous serial interfaces in a systematic manner. The novelty of our approach is to simulate communication across multiple processors in a simulation environment for detecting and localizing bugs. We verify this framework using a case study consisting of an embedded software defined radio (SDR) system. The test results show the applicability of our approach in fixing bugs that relates to synchronization issues that otherwise are very hard to find and fix in very complicated systems, such as SDR.

Multi-Rate Programmable Equalizer for M-PHY Serial Interface

A programmable continuous-time linear equalizer (CTLE) for multi-rate high speed serial interfaces (HSSI) is proposed in this paper. Our solution is compliant with the multi-data rates of 1.45, 2.9, 5.8 and 11.6 Gbps specified by the M-PHY rev.4 HSSI standard for mobile applications. The specifications of the input short-term total jitter STTJ are analyzed demystifying the M-PHY standard. A STTJ generator which is implemented using the behavioral description language cadence verilog-A, is also proposed in order to optimize the CTLE operation and to improve the simulation time for jitter tolerance testing. The transfer function and the power consumption are programmable according to the data-rate and to the frequency band of the STDJ. The CTLE topology was designed and simulated in TSMC CMOS 65 nm process with 1.2 V supply voltage and dissipates 12.5 mA for 11.66 Gbps and the FoM is 0.12 pJ/bit/dB. The output deterministic jitter is around 2.5 ps for 11.66 Gbps.

Experimental evaluation and comparison of latency-optimized opticaland conventional multi-FPGA systems

Rising data rates and input/output density in integrated circuits are challenging the traditional off-chip copper interconnect solutions, demanding a compatible high-speed serial interface capable of maintaining multi-gigabits data rates. Designers typically choose copper interconnect for chip-to-chip connections in a Multi-FPGA System (MFS). However, copper based interconnects are incapable of scaling up with the data rate and exhibit lossy characteristics with increasing frequency. Performance of an MFS can be enhanced if the off-chip electrical interconnects are replaced by short-range optical interconnects. Additionally, the selection of MFS inter-chip communication strategy also affects system performance. We have proposed latency-optimized MFS with serial optical interface with two different inter-chip communication strategies. The proposed architectures were experimentally evaluated using six real world benchmark circuits and provided an average system frequency gain of nearly 22%, compared to conventional MFS.

A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications

A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications

A High-Speed Serial Digital Interface Video Signal Jitter Measurement Method

This paper designs a measurement method for high-speed serial digital interface video signal jitter. Firstly, we introduce the features of SDI signal and the jitter measurement methods of traditional high-speed serial signals. A jitter model is built for the SDI signal while the properties of the components are analysed. An adjusted dual-Dirac model is adopted to measure the jitter in the signal. This method can accurately analyse different jitter components in SDI signals. It is directly performed on oscilloscope, which is beneficial to the traceability of the jitter. The feasibility of the method is verified by experiments. The measurement results show that the method has better measurement accuracy than the direct spectrum method.

A Simple Simulation Approach for the Estimation of Convergence and Performance of Fully Adaptive Equalization in High-Speed Serial Interfaces

We propose a simple approach to simulate the convergence and the performance of high-speed serial interfaces with adaptive equalization. Such a method uses as input the pulse response of the channel (printed circuit board and cables, plus package/socket) that is then modified by adaptive techniques implementing feed-forward, decision-feedback, and linear-continuous time equalization. Probabilistic considerations are used in this novel method to estimate the evolution during time of the LMS loop and the resulting evolution of the eye diagram. Sample results are reported for a realistic link operating at 20 Gb/s.

Implications of On-Chip Single-Source Clocking on High-Speed Serial Interfaces in Network SoC

Editor’s note: Single-source clocking is important for networked SoC architectures. This article discusses the validation challenges related to on-chip single-source clocking due to the distributed clocking trends of recent SoCs and proposes a new low cost and no SoC re-spin solution. —Paul Bogdan, University of Southern California

Evaluation of a high-throughput communication link for future automotive ADAS controllers

The trend toward further integration of automotive electronic control units functionality into domain control units as well as the rise of computing-intensive driver assistance systems has led to a demand for high-performance automotive computation platforms. These platforms have to fulfill stringent safety requirements. One promising approach is the use of performance computation units in combination with safety controllers in a single control unit. Such systems require adequate communication links between the computation units. While Ethernet is widely used, a high-speed serial link communication protocol supported by an Infineon AURIX safety controller appears to be a promising alternative. In this paper, a high-speed serial link IP core is presented, which enables this type of high-speed serial link communication interface for field-programmable gate array–based computing units. In our test setup, the IP core was implemented in a high-performance Xilinx Zynq UltraScale+, which communicated with an Infineon AURIX via high-speed serial link and Ethernet. The first bandwidth measurements demonstrated that high-speed serial link is an interesting candidate for inter-chip communication, resulting in bandwidths reaching up to 127 Mbit/s using stream transmissions.

Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications

This brief presents a fully adaptive high-speed serial interface designed in 28-nm planar CMOS technology for future mobile industry processor interface (MIPI)-compliant automotive microcontrollers operating at 12 Gb/s over long-reach channels. The transmitter has a voltage-mode driver and operates at full rate featuring an 8-tap feed-forward equalizer with tap programmability of 1/16. The transmitter’s output impedance tuning is performed through activation of different driver replicas. The half-rate receiver features an analog front-end which comprises a variable-gain amplifier and a continuous-time linear equalizer. The subsequent decision-feedback equalizer (DFE) has three programmable taps, the first of which is loop-unrolled to relax timing constraints. Another amplifier is embedded in the DFE’s summing node. We employ transistor-level simulations to assess the capability of the interface to optimally adapt to realistic channels: the DFE taps and the data sampling phase are automatically adapted by means of a behavioural implementation of an least mean squares algorithm based on information gathered through error sampling. Such an interface was simulated on channels representing likely MIPI A-PHY to-be-defined specifications featuring up to 33 dB loss at 6 GHz.

A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 ps@2.5 Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor

The equalization of a large attenuation signal and multirate communication in high-speed serial interface is hard to balance. To overcome this difficulty, an adaptive equalization system with optimized eye-opening monitor is proposed. The designed eye-opening monitor is based on the asynchronous statistic eye diagram tracking algorithm, and the eye diagram is obtained by undersampling with the low-speed asynchronous clock. With the eye-opening monitor into the adaptive loop, an adaptive equalization system combined with continuous-time linear equalization (CTLE) is completed. And the inductor peaking technology is used to improve the capacity of compensation. With SMIC 28 nm CMOS process to achieve the overall design, the power consumption and core chip area are 12 mW @ 12.5 Gbps and 0.12 mm2, respectively. And postsimulation results show that it can offer compensation from 6 to 21 dB for 1.25–12.5 Gbps range of receiving data, which achieves a large range of data rate and channel loss, and its power efficiency is 0.046 pJ/bit/dB for the worst case, which is better than most previous works.

Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE

We have designed a high-speed serial interface operating at 9.2 Gb/s for an automotive microcontroller in a 28-nm planar CMOS technology. The full-rate voltage-mode transmitter features an 8-tap feed-forward equalization where each tap can be programmed with steps of 1/16. Impedance tuning is possible by activating different driver replicas. The half-rate receiver features continuous time-linear equalization as well as decision-feedback equalization with 4 taps (one loop-unrolled), along with a dedicated phase-detection algorithm. The final circuit occupies an area of 0.125 mm2 and consumes 5.7 mW/Gb/s under nominal conditions. Experimental characterization demonstrates that the equalization strategies are able to improve the bit error rate well below $10^{-12}$ with typical communication channels for automotive applications.

고속 직렬 인터페이스 커넥터의 설계 및 분석에 대한 연구

고속 직렬 인터페이스 커넥터의 설계 및 분석에 대한 연구

Jitter tolerance calibration for high-speed serial interfaces

A jitter tolerance calibration test bench suitable for high speed serial interfaces (HSSI) using verilog-AMS is proposed in this paper. The jitter tolerance simulation environment can be easily parameterized in order to be compliant to any HSSI standard specification. As an example, the proposed solution is applied for the jitter tolerance simulation and characterization of the most updated M-PHY ver.3 HSSI standard for mobile applications. A comprehensive method for the calculation of the jitter noise frequency ingredients and the calibration of jitter noise sources is also proposed resulting a jitter tolerance mask compliant with the M-PHY ver.3 specifications. Using the proposed implementation the transistor level and behavioral modules co-simulation time could be significantly minimized.

High Speed Serial Interfaces in 2.5D Integrated Systems

Abstract High speed communication has been a topic of great interest in the last decade due to excessively high data rates required between chips especially pushed by the measurement equipment industry to support extremely high bandwidth data sampling. Serial communication is chosen to support these data rates which are pushing further and further into higher data rate regimes. It is important to understand how the 2.5D integration of chips on the interposer can support serial communication and what the designer can do to leverage the special features of interposer channel to achieve lower power and higher speed. This paper will present the interposer complete channel full 3D Electromagnetic simulation based model extraction. It also presents the simulation of channel with real serial communication transmitter and receiver circuit models to describe the proposed interposer performance for multi Gb/s data rates. Also a comparison is shown for different settings of transmitter and receiver circuits under the interposer channel.