Abstract
Abstract High speed communication has been a topic of great interest in the last decade due to excessively high data rates required between chips especially pushed by the measurement equipment industry to support extremely high bandwidth data sampling. Serial communication is chosen to support these data rates which are pushing further and further into higher data rate regimes. It is important to understand how the 2.5D integration of chips on the interposer can support serial communication and what the designer can do to leverage the special features of interposer channel to achieve lower power and higher speed. This paper will present the interposer complete channel full 3D Electromagnetic simulation based model extraction. It also presents the simulation of channel with real serial communication transmitter and receiver circuit models to describe the proposed interposer performance for multi Gb/s data rates. Also a comparison is shown for different settings of transmitter and receiver circuits under the interposer channel.
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